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Forum: FPGA, VHDL & Verilog BlocklyVHDL visual VHDL editor


Author: Hans (Guest)
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Hello,

I found a new type of visual VHDL editor called "blocklyvhdl" on the 
internet. It is a clone of Google's blockly program. You build a VHDL 
program with blocks and then by pressing a button, the code is 
generated.

www.blocklyvhdl.com

Has anyone seen it before? Is it worth to try?

Greetings,

Hans

Author: vhdl ex-pert (Guest)
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not so sure if this is effective.
i played with it 10 minutes now and this is the result:

library STD;
  use IEEE.numeric_std.all;
  use IEEE.std_logic_1164.all;
entity myentity is
   : in  downto ;
   : in  downto ;
   : in  downto ;
end myentity;
architecture a of myentity is
  component name
  end component name;
  signal : ;
begin
  myproc1: process
    variable : ;
  begin
  end process myproc1;
end a;



ok, it saves XML and can be reloaded.
maybe it is interesting when copying and rearanging vhdl blocks , but 
copy and paste also works with normal text based input.

at the moment i do not see a big advantage ...

Author: Fitzebutze (Guest)
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Looks like another educational approach to a language that isn't really 
meant for kids. But the approach is not meant for productive use either.
So I wonder, what should be the target audience. I can't see one.

If I were forced to use blockly in conjunction with logic design, I'd 
rather put the focus on abstraction and debugging. With this current 
approach, it seems you can point/click language elements, but that 
framework is of no use from a designer point of view. And if I were a 
kid, I'd a priori want to see what my language construct is doing, not 
getting confused by language elements.

I gave the thing a go, and just managed in under a minute to create an 
illegal construct. Maybe the author should revisit the idea to match the 
educational block approach with a non-intuitive, heavily complex 
programming language.

Author: Fitzebutze (Guest)
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Maybe I should mention the illegal construct:
entity default is
end default;
architecture default of default is
begin
  signal test: none;
end default;

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