EmbDev.net

Forum: FPGA, VHDL & Verilog Quartus II: How to disable most synthesis optimizations options


Author: Johannes (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hello together,

I'm trying to implement some butterfly-puf-cells on an Altera Cyclone II 
FPGA with Quartus II Version 13.0. But the program always removes my 
latches and connect the output pins to ground.


I have already implemented butterfly-puf-cells on a Xilinx Spartan3e 
FPGA with Xilinx ISE and using the same vhdl-files and it worked just 
fine.


You can find my Quartus-Project above. I'm really looking forward for 
your answers!

Thanks in advance

Johannes

: Restored by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig