Forum: FPGA, VHDL & Verilog Generating SAIF file

von dayana42200 (Guest)

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Hello everyone.

Im wanted to generate the SAIF file from ISIM. Im using Xilinx ISE 
Design Suite 14.7

Ive found the method to generate SAIF file.Please also refer to the 
attach figure.

1. Implement the top module

2. Generate post-place and route simulation model.

3. Now change to simulation mode then change to post route and click the 
generate post-place and route simulation model.

4. Click simulate post-place and route model.

However, there is an error.

>WARNING:HDLCompiler:929 - 
netgen/par/ProcessingElement_timesim.v"  Line 6097: Top-level design unit glbl 
specified more than once, ignoring glbl of library work
>ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in 
library work failed

Please help me to solve the error  or any other method to generate SAIF 

Thank you very much.

von vhdl ex-pert (Guest)

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i tried several times to run the power analysis with ISE this way and 
always failed. creating and using saif files is not straigth forward and 
meets the typical chaotic way of working which is well known with 

i finally gave up to work with their tool and use it only when 
absolutely necessary.

we shunned IDE finally and switched totally to Altera

in the meanwhile i could commit that vivado does much better and i did 
some projects but my current company refuses to switch back to xilinx 
because transforming designs always leads to a bunch of work.


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