Im wanted to generate the SAIF file from ISIM. Im using Xilinx ISE
Design Suite 14.7
Ive found the method to generate SAIF file.Please also refer to the
1. Implement the top module
2. Generate post-place and route simulation model.
3. Now change to simulation mode then change to post route and click the
generate post-place and route simulation model.
4. Click simulate post-place and route model.
However, there is an error.
netgen/par/ProcessingElement_timesim.v" Line 6097: Top-level design unit glbl
specified more than once, ignoring glbl of library work
>ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in
library work failed
Please help me to solve the error or any other method to generate SAIF
Thank you very much.