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Forum: FPGA, VHDL & Verilog VHDL multiplication for std_logic_vector


von Miguel (Guest)


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When simulating I get a run time error, so I'm trying to run a RTL 
analysis in Vivado to see if the schematic of the component can be 
created at least. The code is the following
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity multiplicator_test is
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  generic(
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      WORD_SIZE: natural := 8;
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      EXP_SIZE: natural := 3
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    );
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    port(
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      input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
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      input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
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      result: out std_logic_vector(WORD_SIZE-1 downto 0)
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    );
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end entity multiplicator_test;
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architecture multiplicator_test_arch of multiplicator_test is
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  constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;
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  signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
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  signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
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  signal sign: std_logic := '0';
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  signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
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begin
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    aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
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    significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
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    exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
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    sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
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    result <= sign & exponent & significand;
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end architecture multiplicator_test_arch;

When running the analysis, I get
1
ERROR: [Synth 8-690] width mismatch in assignment; target has 3 bits, source has 4 bits [(...)/multiplicador.vhd:27]

The line with the error is 27,
1
aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));

Apparently the target (aux) is 3 bits, but really it should be 8.

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