When simulating I get a run time error, so I'm trying to run a RTL
analysis in Vivado to see if the schematic of the component can be
created at least. The code is the following
1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use IEEE.numeric_std.all;
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4 |
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5 | entity multiplicator_test is
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6 | generic(
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7 | WORD_SIZE: natural := 8;
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8 | EXP_SIZE: natural := 3
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9 | );
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10 | port(
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11 | input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
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12 | input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
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13 | result: out std_logic_vector(WORD_SIZE-1 downto 0)
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14 | );
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15 | end entity multiplicator_test;
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16 |
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17 | architecture multiplicator_test_arch of multiplicator_test is
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18 | constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;
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19 |
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20 | signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
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21 | signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
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22 | signal sign: std_logic := '0';
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23 | signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
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24 | begin
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25 | aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
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26 | significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
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27 | exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
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28 | sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
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29 | result <= sign & exponent & significand;
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30 | end architecture multiplicator_test_arch;
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When running the analysis, I get
1 | ERROR: [Synth 8-690] width mismatch in assignment; target has 3 bits, source has 4 bits [(...)/multiplicador.vhd:27]
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The line with the error is 27,
1 | aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
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Apparently the target (aux) is 3 bits, but really it should be 8.
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