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Forum: FPGA, VHDL & Verilog Datapath 8 bits VHDL Modelsim


Author: KleinBagel (Guest)
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Bonjour,
Depuis plusieurs jours j’essaye de savoir pourquoi la simulation 
modelsim m’affiche pour output :UUUUU
Si quelqu’un peut m'aider a comprendre
Voici la capture d'écran de modelsim : https://prnt.sc/l6dtin
Voici les codes pour les différents composants:
-- datapath .vhd

library ieee ;
use ieee.std_logic_1164.all ;
use work.pack.all;

entity datapath is port( clk: in std_logic;
                 input: in std_logic_vector(7 downto 0);
                 ie: in std_logic;
                 we: in std_logic;
                 wa: in std_logic_vector(1 downto 0);
                 rae: in std_logic;
                 raa: in std_logic_vector(1 downto 0);
                 rbe: in std_logic;
                 rba: in std_logic_vector(1 downto 0);
                 opcode: in std_logic_vector(2 downto 0);
                 shsel: in std_logic_vector(1 downto 0);
                 oe: in std_logic;
                 output: out std_logic_vector(7 downto 0));
end datapath ;
architecture behavior of datapath is

signal muxout, rfAout, rfBout: std_logic_vector(7 downto 0);
signal aluout, shiftout, tristateout: std_logic_vector(7 downto 0);

begin
U0: mux2 port map( ie, input, shiftout, muxout );
U1: regfile port map(clk,we,wa,muxout,rae,raa,rbe,rba,rfAout,rfBout );
U2: alu port map( opcode, rfAout, rfBout, aluout );
U3: shifter port map(shsel,aluout,shiftout);
U4: tristatebuffer port map(oe, shiftout, tristateout);
output <= tristateout;
end behavior;

-- mux2 .vhd

library ieee ;
use ieee.std_logic_1164.all ;

entity mux2 is port( s: in std_logic;                   -- select line
              d1, d0: in std_logic_vector(7 downto 0);   -- data bus input
              y: out std_logic_vector(7 downto 0));     -- data bus output
end mux2;
architecture behavior of mux2 is
  begin
    process(s, d1, d0)
      begin
        if(s = '0')then
          y <= d0;
        else
          y <= d1;
        end if;
    end process;
end behavior;

-- regfile .vhd

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity regfile is port( clk: in std_logic;                     --clock
                we: in std_logic;                     --write enable WE
                wa: in std_logic_vector(1 downto 0);         --write address WA
                input: in std_logic_vector(7 downto 0);       --input
                rae: in std_logic;                     --read enable port A 
                raa: in std_logic_vector(1 downto 0);         --read address port A
                rbe: in std_logic;                     --read enable port B
                rba: in std_logic_vector(1 downto 0);         --read address port B
                Aout, Bout: out std_logic_vector(7 downto 0));  --output port A & B
end regfile;
architecture behavior of regfile is
    subtype reg is std_logic_vector(7 downto 0);
    type regArray is array(0 to 3) of reg;
    signal rf: regArray; --register file contents
  begin
    WritePort: process(clk)
  begin
    if (clk'event and clk = '1')then
      if (we = '1')then
        rf(to_integer(unsigned(wa))) <= input;
      end if;
    end if;
  end process;
    ReadPortA: process(rae, raa)
  begin
    if (rae = '1') then
      Aout <= rf(to_integer(unsigned(raa))); -- convert bit VECTOR to integer
    else
      Aout <= (others => '0');
    end if;
  end process;
    ReadPortB: process(rbe, rba)
  begin
    if (rbe = '1') then
      Bout <= rf(to_integer(unsigned(rba))); -- convert bit VECTOR to integer
    else
      Bout <= (others => '0');
    end if;
  end process;
end behavior;

-- alu .vhd

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;

entity alu is port( opcode: in std_logic_vector(2 downto 0);   -- select for operations
              a, b: in std_logic_vector(7 downto 0);     -- input operands
              f: out std_logic_vector(7 downto 0));     -- output
end alu;
architecture behavior of alu is
  begin
  PROCESS(opcode, a, b)
    begin
    case opcode is
    when "000" => f <= a;      -- pass
    when "001" => f <= a and b;  -- and
    when "010" => f <= a or b;    -- or
    when "011" => f <= not b;    -- not
    when "100" => f <= a + b;    -- add
    when "101" => f <= a - b;    -- substact
    when "110" => f <= a + 1;    -- increment
    when "111" => f <= a - 1;    -- decrement
    when others => f <= (others => '0');
    end case;
  end process;
end behavior;

-- shifter .vhd

library ieee ;
use ieee.std_logic_1164.all ;

entity shifter is port( shsel: in std_logic_vector(1 downto 0);     -- select for operations
                input: in std_logic_vector(7 downto 0);     -- input operands
                output: out std_logic_vector(7 downto 0));   -- output
end shifter;
architecture behavior of shifter is
  begin
  process(shsel, input)
  begin
    case shsel is
    when "00" => output <= input;                 -- pass
    when "01" => output <= input(6 downto 0) & '0';     -- shift right
    when "10" => output <= '0' & input(7 downto 1);     -- shift left
    when "11" => output <= input(0) & input(7 downto 1);  -- rotate right
    when others => output <= (others => '0'); 
    end case;
  end process;
end behavior;

-- tristatebuffer .vhd

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tristatebuffer is port( e: in std_logic;               -- single buffer input
                     d: in std_logic_vector(7 downto 0);  -- single buffer enable
                     y: out std_logic_vector(7 downto 0));  -- single buffer output
end tristatebuffer;
architecture behavior of tristatebuffer is
  begin
  process (e, d) -- get error message if no d
  begin
    if (e = '1')then
      y <= d;
    else
      y <= (others => 'Z'); -- to get 8 Z values
    end if;
  end process;
end behavior;

-- datapath_tb .vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity datapath_tb is
end datapath_tb;
 
architecture behavior of datapath_tb is
-- Component Declaration for the Unit Under Test (UUT)
component datapath port( clk: in std_logic;
                 input: in std_logic_vector(7 downto 0);
                 ie: in std_logic;
                 we: in std_logic;
                 wa: in std_logic_vector(1 downto 0);
                 rae: in std_logic;
                 raa: in std_logic_vector(1 downto 0);
                 rbe: in std_logic;
                 rba: in std_logic_vector(1 downto 0);
                 opcode: in std_logic_vector(2 downto 0);
                 shsel: in std_logic_vector(1 downto 0);
                 oe: in std_logic;
                 output: out std_logic_vector(7 downto 0));
end component;
  --inputs
  signal clk : std_logic := '0';
  signal input : std_logic_vector(7 downto 0) := (others => '0');
  signal ie : std_logic := '0';
  signal we : std_logic := '0';
  signal wa : std_logic_vector(1 downto 0) := (others => '0');
  signal rae : std_logic := '0';
  signal raa : std_logic_vector(1 downto 0) := (others => '0');
  signal rbe : std_logic := '0';
  signal rba : std_logic_vector(1 downto 0) := (others => '0');
  signal opcode : std_logic_vector(2 downto 0) := (others => '0');
  signal shsel : std_logic_vector(1 downto 0) := (others => '0');
  signal oe : std_logic := '0';
  --Outputs
  signal output : std_logic_vector(7 downto 0);
  -- Clock period definitions
  constant clock_period : time := 50 ns;
  
  begin
  
  -- Instantiate the Unit Under Test (UUT)
  uut: datapath port map(clk, input, ie, we, wa, rae, raa, rbe, rba, opcode, shsel, oe, output);
  
  -- Clock process definitions
  clock_process :process
  begin
    clk <= '0';
    wait for clock_period/2;
    clk <= '1';
    wait for clock_period/2;
  end process;
  
  -- Stimulus process
  stim_proc: process
  begin  
  -- hold reset state for 100 ns.
  --Initialize inputs
  
    input <= "00000000";      -- input binary 4
    ie <= '0';               --input enabled
    wa <= "00";           -- input stored in address binary 0
    we <= '0';            --write enabled
    raa <= "00";
    rae <= '0';
    rba <= "00";
    rbe <= '0';
    opcode <= "000";
    shsel <= "00";
    oe <= '0';
      
    wait for 50 ns;
    input <= "00000100";    -- input binary 4
    ie <= '1';             --input enabled
    wa <= "00";         -- input stored in address binary 0
    we <= '1';          --write enabled
    raa <= "00";
    rae <= '0';
    rba <= "00";
    rbe <= '0';
    opcode <= "000";
    shsel <= "00";
    oe <= '0';
     
    wait for 50 ns;
    input <= "00000000";
    ie <= '0';
    wa <= "01";      --store result of the operation done in the ALU in address binary 1 the result is 1000
    we <= '1';      --write in address enabled
    raa <= "00";      --read address 0 in A
    rae <= '1';      --read enabled
    rba <= "00";      --read address 0 in B
    rbe <= '1';      --read enabled
    opcode <= "100";  --add A + B = 100+100=1000
    shsel <= "00";
    oe  <= '1';
    
    -- insert stimulus here 

    wait;
    end process;

end;

--addresses 00 = 00000100 binary 4
--addresses 01 = 00001000 result binary 8 
--addresses 10
--addresses 11

--pack. vhd

library ieee ;
use ieee.std_logic_1164.all ;
package pack is
component mux2 port(  s: in std_logic;                   -- select lines
              d1, d0: in std_logic_vector(7 downto 0);   -- data bus input
              y: out std_logic_vector(7 downto 0));    -- data bus output
end component;
component regfile port( clk: in std_logic;                     --clock
                we: in std_logic;                     --write enable WE
                wa: in std_logic_vector(1 downto 0);         --write address WA
                input: in std_logic_vector(7 downto 0);       --input
                rae: in std_logic;                     --read enable port A
                raa: in std_logic_vector(1 downto 0);         --read address port A
                rbe: in std_logic;                     --read enable port B
                rba: in std_logic_vector(1 downto 0);         --read address port B
                Aout, Bout: out std_logic_vector(7 downto 0));  --output port A & B
end component;
component alu port( opcode: in std_logic_vector(2 downto 0);   -- select for operations
              a, b: in std_logic_vector(7 downto 0);     -- input operands
              f: out std_logic_vector(7 downto 0));     -- output
end component;
component shifter port( shsel: in std_logic_vector(1 downto 0);     -- select for operations
                input: in std_logic_vector(7 downto 0);     -- input operands
                output: out std_logic_vector(7 downto 0));   -- output
end component;
component tristatebuffer port( e: in std_logic;               -- single buffer input
                     d: in std_logic_vector(7 downto 0);  -- single buffer enable
                     y: out std_logic_vector(7 downto 0));  -- single buffer output
end component;
end pack ;

Author: Jürgen S. (engineer)
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Salut

au début, je bien voudrais dire que ce n'est pas bon avec les 4 
bibliothèques, ils pourraient se déranger. Aussi les nombreux paramètres 
derrière le signal clock dans la liste de sensibilité peut faire des 
problèmes.

Je ne suis pas sûr, quel est le problème exact mais si seulement la 
simulation fait des problèmes, c'est souvent un compteur qui n'est pas 
initialisé.

Author: KleinBagel (Guest)
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the problem is the output signal here is what I should have
http://prntscr.com/l6t2fi

Author: Zim A. (zim_a)
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can u provide code for this plsss ..
https://dltutuapp.com/
https://9apps.ooo/
https://showbox.run/

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