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Forum: FPGA, VHDL & Verilog Datapath 8 bits VHDL Modelsim


von KleinBagel (Guest)


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Bonjour,
Depuis plusieurs jours j’essaye de savoir pourquoi la simulation 
modelsim m’affiche pour output :UUUUU
Si quelqu’un peut m'aider a comprendre
Voici la capture d'écran de modelsim : https://prnt.sc/l6dtin
Voici les codes pour les différents composants:
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-- datapath .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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use work.pack.all;
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entity datapath is port( clk: in std_logic;
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                 input: in std_logic_vector(7 downto 0);
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                 ie: in std_logic;
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                 we: in std_logic;
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                 wa: in std_logic_vector(1 downto 0);
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                 rae: in std_logic;
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                 raa: in std_logic_vector(1 downto 0);
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                 rbe: in std_logic;
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                 rba: in std_logic_vector(1 downto 0);
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                 opcode: in std_logic_vector(2 downto 0);
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                 shsel: in std_logic_vector(1 downto 0);
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                 oe: in std_logic;
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                 output: out std_logic_vector(7 downto 0));
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end datapath ;
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architecture behavior of datapath is
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signal muxout, rfAout, rfBout: std_logic_vector(7 downto 0);
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signal aluout, shiftout, tristateout: std_logic_vector(7 downto 0);
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begin
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U0: mux2 port map( ie, input, shiftout, muxout );
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U1: regfile port map(clk,we,wa,muxout,rae,raa,rbe,rba,rfAout,rfBout );
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U2: alu port map( opcode, rfAout, rfBout, aluout );
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U3: shifter port map(shsel,aluout,shiftout);
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U4: tristatebuffer port map(oe, shiftout, tristateout);
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output <= tristateout;
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end behavior;
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-- mux2 .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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entity mux2 is port( s: in std_logic;                   -- select line
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              d1, d0: in std_logic_vector(7 downto 0);   -- data bus input
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              y: out std_logic_vector(7 downto 0));     -- data bus output
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end mux2;
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architecture behavior of mux2 is
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  begin
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    process(s, d1, d0)
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      begin
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        if(s = '0')then
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          y <= d0;
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        else
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          y <= d1;
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        end if;
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    end process;
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end behavior;
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-- regfile .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity regfile is port( clk: in std_logic;                     --clock
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                we: in std_logic;                     --write enable WE
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                wa: in std_logic_vector(1 downto 0);         --write address WA
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                input: in std_logic_vector(7 downto 0);       --input
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                rae: in std_logic;                     --read enable port A 
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                raa: in std_logic_vector(1 downto 0);         --read address port A
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                rbe: in std_logic;                     --read enable port B
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                rba: in std_logic_vector(1 downto 0);         --read address port B
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                Aout, Bout: out std_logic_vector(7 downto 0));  --output port A & B
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end regfile;
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architecture behavior of regfile is
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    subtype reg is std_logic_vector(7 downto 0);
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    type regArray is array(0 to 3) of reg;
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    signal rf: regArray; --register file contents
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  begin
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    WritePort: process(clk)
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  begin
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    if (clk'event and clk = '1')then
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      if (we = '1')then
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        rf(to_integer(unsigned(wa))) <= input;
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      end if;
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    end if;
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  end process;
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    ReadPortA: process(rae, raa)
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  begin
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    if (rae = '1') then
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      Aout <= rf(to_integer(unsigned(raa))); -- convert bit VECTOR to integer
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    else
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      Aout <= (others => '0');
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    end if;
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  end process;
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    ReadPortB: process(rbe, rba)
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  begin
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    if (rbe = '1') then
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      Bout <= rf(to_integer(unsigned(rba))); -- convert bit VECTOR to integer
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    else
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      Bout <= (others => '0');
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    end if;
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  end process;
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end behavior;
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-- alu .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_unsigned.all;
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entity alu is port( opcode: in std_logic_vector(2 downto 0);   -- select for operations
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              a, b: in std_logic_vector(7 downto 0);     -- input operands
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              f: out std_logic_vector(7 downto 0));     -- output
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end alu;
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architecture behavior of alu is
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  begin
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  PROCESS(opcode, a, b)
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    begin
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    case opcode is
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    when "000" => f <= a;      -- pass
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    when "001" => f <= a and b;  -- and
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    when "010" => f <= a or b;    -- or
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    when "011" => f <= not b;    -- not
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    when "100" => f <= a + b;    -- add
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    when "101" => f <= a - b;    -- substact
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    when "110" => f <= a + 1;    -- increment
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    when "111" => f <= a - 1;    -- decrement
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    when others => f <= (others => '0');
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    end case;
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  end process;
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end behavior;
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-- shifter .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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entity shifter is port( shsel: in std_logic_vector(1 downto 0);     -- select for operations
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                input: in std_logic_vector(7 downto 0);     -- input operands
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                output: out std_logic_vector(7 downto 0));   -- output
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end shifter;
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architecture behavior of shifter is
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  begin
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  process(shsel, input)
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  begin
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    case shsel is
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    when "00" => output <= input;                 -- pass
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    when "01" => output <= input(6 downto 0) & '0';     -- shift right
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    when "10" => output <= '0' & input(7 downto 1);     -- shift left
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    when "11" => output <= input(0) & input(7 downto 1);  -- rotate right
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    when others => output <= (others => '0'); 
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    end case;
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  end process;
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end behavior;
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-- tristatebuffer .vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity tristatebuffer is port( e: in std_logic;               -- single buffer input
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                     d: in std_logic_vector(7 downto 0);  -- single buffer enable
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                     y: out std_logic_vector(7 downto 0));  -- single buffer output
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end tristatebuffer;
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architecture behavior of tristatebuffer is
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  begin
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  process (e, d) -- get error message if no d
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  begin
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    if (e = '1')then
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      y <= d;
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    else
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      y <= (others => 'Z'); -- to get 8 Z values
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    end if;
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  end process;
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end behavior;
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-- datapath_tb .vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity datapath_tb is
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end datapath_tb;
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architecture behavior of datapath_tb is
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-- Component Declaration for the Unit Under Test (UUT)
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component datapath port( clk: in std_logic;
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                 input: in std_logic_vector(7 downto 0);
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                 ie: in std_logic;
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                 we: in std_logic;
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                 wa: in std_logic_vector(1 downto 0);
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                 rae: in std_logic;
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                 raa: in std_logic_vector(1 downto 0);
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                 rbe: in std_logic;
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                 rba: in std_logic_vector(1 downto 0);
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                 opcode: in std_logic_vector(2 downto 0);
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                 shsel: in std_logic_vector(1 downto 0);
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                 oe: in std_logic;
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                 output: out std_logic_vector(7 downto 0));
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end component;
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  --inputs
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  signal clk : std_logic := '0';
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  signal input : std_logic_vector(7 downto 0) := (others => '0');
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  signal ie : std_logic := '0';
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  signal we : std_logic := '0';
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  signal wa : std_logic_vector(1 downto 0) := (others => '0');
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  signal rae : std_logic := '0';
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  signal raa : std_logic_vector(1 downto 0) := (others => '0');
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  signal rbe : std_logic := '0';
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  signal rba : std_logic_vector(1 downto 0) := (others => '0');
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  signal opcode : std_logic_vector(2 downto 0) := (others => '0');
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  signal shsel : std_logic_vector(1 downto 0) := (others => '0');
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  signal oe : std_logic := '0';
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  --Outputs
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  signal output : std_logic_vector(7 downto 0);
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  -- Clock period definitions
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  constant clock_period : time := 50 ns;
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  begin
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  -- Instantiate the Unit Under Test (UUT)
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  uut: datapath port map(clk, input, ie, we, wa, rae, raa, rbe, rba, opcode, shsel, oe, output);
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  -- Clock process definitions
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  clock_process :process
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  begin
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    clk <= '0';
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    wait for clock_period/2;
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    clk <= '1';
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    wait for clock_period/2;
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  end process;
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  -- Stimulus process
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  stim_proc: process
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  begin  
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  -- hold reset state for 100 ns.
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  --Initialize inputs
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    input <= "00000000";      -- input binary 4
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    ie <= '0';               --input enabled
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    wa <= "00";           -- input stored in address binary 0
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    we <= '0';            --write enabled
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    raa <= "00";
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    rae <= '0';
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    rba <= "00";
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    rbe <= '0';
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    opcode <= "000";
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    shsel <= "00";
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    oe <= '0';
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    wait for 50 ns;
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    input <= "00000100";    -- input binary 4
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    ie <= '1';             --input enabled
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    wa <= "00";         -- input stored in address binary 0
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    we <= '1';          --write enabled
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    raa <= "00";
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    rae <= '0';
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    rba <= "00";
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    rbe <= '0';
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    opcode <= "000";
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    shsel <= "00";
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    oe <= '0';
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    wait for 50 ns;
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    input <= "00000000";
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    ie <= '0';
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    wa <= "01";      --store result of the operation done in the ALU in address binary 1 the result is 1000
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    we <= '1';      --write in address enabled
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    raa <= "00";      --read address 0 in A
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    rae <= '1';      --read enabled
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    rba <= "00";      --read address 0 in B
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    rbe <= '1';      --read enabled
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    opcode <= "100";  --add A + B = 100+100=1000
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    shsel <= "00";
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    oe  <= '1';
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    -- insert stimulus here 
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    wait;
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    end process;
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end;
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--addresses 00 = 00000100 binary 4
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--addresses 01 = 00001000 result binary 8 
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--addresses 10
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--addresses 11
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--pack. vhd
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library ieee ;
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use ieee.std_logic_1164.all ;
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package pack is
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component mux2 port(  s: in std_logic;                   -- select lines
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              d1, d0: in std_logic_vector(7 downto 0);   -- data bus input
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              y: out std_logic_vector(7 downto 0));    -- data bus output
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end component;
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component regfile port( clk: in std_logic;                     --clock
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                we: in std_logic;                     --write enable WE
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                wa: in std_logic_vector(1 downto 0);         --write address WA
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                input: in std_logic_vector(7 downto 0);       --input
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                rae: in std_logic;                     --read enable port A
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                raa: in std_logic_vector(1 downto 0);         --read address port A
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                rbe: in std_logic;                     --read enable port B
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                rba: in std_logic_vector(1 downto 0);         --read address port B
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                Aout, Bout: out std_logic_vector(7 downto 0));  --output port A & B
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end component;
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component alu port( opcode: in std_logic_vector(2 downto 0);   -- select for operations
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              a, b: in std_logic_vector(7 downto 0);     -- input operands
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              f: out std_logic_vector(7 downto 0));     -- output
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end component;
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component shifter port( shsel: in std_logic_vector(1 downto 0);     -- select for operations
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                input: in std_logic_vector(7 downto 0);     -- input operands
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                output: out std_logic_vector(7 downto 0));   -- output
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end component;
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component tristatebuffer port( e: in std_logic;               -- single buffer input
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                     d: in std_logic_vector(7 downto 0);  -- single buffer enable
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                     y: out std_logic_vector(7 downto 0));  -- single buffer output
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end component;
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end pack ;

von Jürgen S. (engineer)


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Salut

au début, je bien voudrais dire que ce n'est pas bon avec les 4 
bibliothèques, ils pourraient se déranger. Aussi les nombreux paramètres 
derrière le signal clock dans la liste de sensibilité peut faire des 
problèmes.

Je ne suis pas sûr, quel est le problème exact mais si seulement la 
simulation fait des problèmes, c'est souvent un compteur qui n'est pas 
initialisé.

von KleinBagel (Guest)


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the problem is the output signal here is what I should have
http://prntscr.com/l6t2fi

von Zim A. (zim_a)


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can u provide code for this plsss ..
https://dltutuapp.com/
https://9apps.ooo/
https://showbox.run/

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