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Forum: FPGA, VHDL & Verilog Dont care in Array assignment


Author: HO Man Chan (Guest)
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In modelsim, when I assign a std logic vector(din) to an element (r_reg) 
in n array of std logic vector, it give me dont cares for 1's and 0 for 
0's. Why are the 1's dont care and how to fix it?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity regfile is
  port (
    din: in std_logic_vector(31 downto 0);
    write_address, read_a, read_b: in std_logic_vector(4 downto 0);
    reset, clk, write: in std_logic;
    out_a, out_b: out std_logic_vector(31 downto 0)
  );
end regfile;

architecture structural of regfile is

-- declare components
-- end declare component

-- declare signals used to connect components
type t_reg is array (0 to 31) of std_logic_vector(31 downto 0);
signal r_reg : t_reg := (others => (others => '0'));
-- end declare signals used to connect components

-- declare configuration specification
-- end declare configuration specification

begin

-- init component
-- end init component

r_reg <= (others => (others => '0')) when reset='1';
out_a <= r_reg(to_integer(unsigned(read_a)));
out_b <= r_reg(to_integer(unsigned(read_b)));

process(clk, write, write_address, din)
begin
  if (clk'event and clk='1') then
    if (write='1') then
      r_reg(to_integer(unsigned(write_address))) <= din;
    end if;
  end if;
end process;

end structural;

# do file to test the regfile
add wave reset
add wave clk
add wave din
add wave write
add wave read_a
add wave read_b
add wave write_address
add wave out_a
add wave out_b
add wave r_reg

# reset
force reset 1
force clk 0
force din X"FAFA3B3B"
force write 0
force write_address "00001"
force read_a "00000"
force read_b "00001"
run 2

#deassert reset and write into R1
force reset 0
run 2
force write 1
run 2
force clk 1
run 2
force clk 0
run 2

# write X"FAFA3B3B" into R31 and sent R31 to both out ports
force write_address "11110"
run 2
force read_a "11110"
force read_b "11110"
force clk 1
run 2
force clk 0
run 2

# deassert write, and try to write new data into R31, shouild be
no change
force write 0
run 2
force clk 1
run 2
force clk 0
run 2

# write data into R1-R31 consecutively
force write 1
force write_address "00001"
force din X"00000001"
force clk 1
run 2
force clk 0
run 2

force write_address "00010"
force din X"00000002"
force clk 1
run 2
force clk 0
run 2

force write_address "00011"
force din X"00000003"
force clk 1
run 2
force clk 0
run 2

force write_address "00100"
force din X"00000004"
force clk 1
run 2
force clk 0
run 2

force write_address "00101"
force din X"00000005"
force clk 1
run 2
force clk 0
run 2

force write_address "00110"
force din X"00000006"
force clk 1
run 2
force clk 0
run 2


force write_address "00111"
force din X"00000007"
force clk 1
run 2
force clk 0
run 2

force write_address "01000"
force din X"00000008"
force clk 1
run 2
force clk 0
run 2

force write_address "01001"
force din X"00000009"
force clk 1
run 2
force clk 0
run 2

force write_address "01010"
force din X"0000000A"
force clk 1
run 2
force clk 0
run 2

force write_address "01011"
force din X"0000000B"
force clk 1
run 2
force clk 0
run 2

force write_address "01100"
force din X"0000000C"
force clk 1
run 2
force clk 0
run 2

force write_address "01101"
force din X"0000000D"
force clk 1
run 2
force clk 0
run 2

force write_address "01110"
force din X"0000000E"
force clk 1
run 2
force clk 0
run 2

force write_address "01111"
force din X"0000000F"
force clk 1
run 2
force clk 0
run 2

# second hald of registers

force write_address "10000"
force din X"00000010"
force clk 1
run 2
force clk 0
run 2

force write_address "10001"
force din X"00000011"
force clk 1
run 2
force clk 0
run 2

force write_address "10010"
force din X"00000012"
force clk 1
run 2
force clk 0
run 2

force write_address "10011"
force din X"00000013"
force clk 1
run 2
force clk 0
run 2

force write_address "10100"
force din X"00000014"
force clk 1
run 2
force clk 0
run 2

force write_address "10101"
force din X"00000015"
force clk 1
run 2
force clk 0
run 2

force write_address "10110"
force din X"00000016"
force clk 1
run 2
force clk 0
run 2

force write_address "10111"
force din X"00000017"
force clk 1
run 2
force clk 0
run 2

force write_address "10001"
force din X"00000011"
force clk 1
run 2
force clk 0
run 2

force write_address "11000"
force din X"00000018"
force clk 1
run 2
force clk 0
run 2

force write_address "11001"
force din X"00000019"
force clk 1
run 2
force clk 0
run 2

force write_address "11011"
force din X"0000001B"
force clk 1
run 2
force clk 0
run 2

force write_address "11100"
force din X"0000001C"
force clk 1
run 2
force clk 0
run 2

force write_address "11101"
force din X"0000001D"
force clk 1
run 2
force clk 0
run 2

force write_address "11110"
force din X"0000001E"
force clk 1
run 2
force clk 0
run 2

force write_address "11111"
force din X"0000001F"
force clk 1
run 2
force clk 0
run 2

# now deassert the write and read out consecutively asynchronously

force write 0
force read_a "00000"
force read_b "00001"
run 2

force read_a "00001"
force read_b "00010"
run 2

force read_a "00011"
force read_b "00100"
run 2

force read_a "00100"
force read_b "00101"
run 2

force read_a "00110"
force read_b "00111"
run 2

force read_a "00111"
force read_b "01000"
run 2

force read_a "01001"
force read_b "01010"
run 2

force read_a "01011"
force read_b "01100"
run 2

force read_a "01101"
force read_b "01110"
run 2

force read_a "01111"
force read_b "10000"
run 2

# second half of reads

force read_a "10001"
force read_b "10010"
run 2

force read_a "10011"
force read_b "10100"
run 2

force read_a "10101"
force read_b "10110"
run 2

force read_a "10111"
force read_b "11000"
run 2

force read_a "11001"
force read_b "11010"
run 2

force read_a "11011"
force read_b "11100"
run 2

# next 3 quarter
force read_a "11101"
force read_b "11110"
run 2

force read_a "11111"
force read_b "11111"
run 2

Author: Dussel (Guest)
Posted on:

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There are tags for code formatting, as mentioned above the text field. 
Then the code is readable.

I bet that there is no don't care as a result.

You have two assignments to r_reg simultaneously. That will result in a 
conflict ('X' as value and red lines in modelsim), when different values 
are assigned.

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