Hello everyone,

I am a beginner in Verilog. Here's a simple code for behavioral 
modeling:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

module first_system(out1,out2,in1,in2);

// Port definitions
input in1,in2;
output out1,out2;

// Description of the digital system
// Behavioral modeling

reg  out1,out2;

initial
begin
out1 = 0;
out2 = 0;
end

always @ (in1, in2)
begin
out1 = (in1 & in2) ^ (in1 | in2);
out2 = ~ in2;
end

endmodule

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Now the textbook says that "The always keyword executes the beneath 
description block (encapsulated by begin and end keywords) 
whenever in1 or in2 changes. If there is no change in these variables, 
output will not be provided by the system."


Here out1 and out2 are two LEDs and in1 and in2 are two switches. So my 
understanding is since out1 and out2 are intialized as 0s, the two LEDs 
should be both off until we toggle the switches. However, after I 
program it to a Basys3 board, the LEDs can be on in the very beginning 
even if I haven't done anything to the switches.


So my question is: did I misunderstand anything in here? Also, is there 
a way to let the board not show any outputs (not turn on any LEDs) until 
we change the states of the switches?


Thank you so much in advance!!!