Hi, I have written simple verilog code for counter. But i dont need that. I need to control FIFO from counter block. Please find the attachment of counter and FIFO design. I need to control the FIFO__in_write signal only. I want to change the design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full. I need help in Verilog coding part.
Can't help you with Verilog. But I think, you just want to compare the value of counter with your FIFO size. Doing this in Verilog should not be a problem for you. If it is - post your code that did not work. I am pretty sure someone out there will find your mistake.
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