Counter and Alter FIFO using VHDL/Verilog

Saraswathy S. (saras015) OP 2018-09-14 07:55 #5555862

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Hi,

   I have written simple verilog code for counter. But i dont need that.

I need to control FIFO from counter block.

Please find the attachment of counter and FIFO design.

I need to control the FIFO__in_write signal only.

I want to change the design to check whether the fifo is full or not and 
only write the value (and increment the counter) when the fifo is not 
full.

 I need help in Verilog coding part.

Attached files:

FIFO_design.JPG (260 KB)

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VHDL Guest 2018-09-14 12:01 #5556107

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Can't help you with Verilog. But I think, you just want to compare the 
value of counter with your FIFO size. Doing this in Verilog should not 
be a problem for you. If it is - post your code that did not work. I am 
pretty sure someone out there will find your mistake.

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Maddhura S. (madhura) (Company: Maven Silicon) 2018-09-14 15:19 #5556310

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You can also refer to the video https://youtu.be/uUZceAfnVNk for a great 
understanding of #verilog. This tutorial covers registers, unwanted 
latches & operator synthesis and helps you master these fundamental 
concepts.Check out the series of free tutorials by Mr. P R 
Sivakumar(CEO, Maven Silicon) on basic and advanced concepts of Front 
End VLSI. His amazing explanations and easy to understand content make 
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