Hi, I have written simple verilog code for counter. But i dont need that. I need to control FIFO from counter block. Please find the attachment of counter and FIFO design. I need to control the FIFO__in_write signal only. I want to change the design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full. I need help in Verilog coding part.
Can't help you with Verilog. But I think, you just want to compare the value of counter with your FIFO size. Doing this in Verilog should not be a problem for you. If it is - post your code that did not work. I am pretty sure someone out there will find your mistake.
You can also refer to the video https://youtu.be/uUZceAfnVNk for a great understanding of #verilog. This tutorial covers registers, unwanted latches & operator synthesis and helps you master these fundamental concepts.Check out the series of free tutorials by Mr. P R Sivakumar(CEO, Maven Silicon) on basic and advanced concepts of Front End VLSI. His amazing explanations and easy to understand content make these videos a great tool for you to update and upgrade your VLSI skills.
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.