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Forum: FPGA, VHDL & Verilog Verilog Data Type


Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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I have an 32-bit reg 'count' that stores a large integer value. I intend 
to divide it by 14800 and store the result in a data type which is 8 
bits (So values from 0-255) and is unsigned. If the result is something 
like 1.4, it must be rounded of to the nearest integer, in this case 1.

What is the best way of doing this.

- Thanks in advance.

Author: Andy (Guest)
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Dividing by a constant can often be done by multiplying with the 
reciprocal value. Here you need to scale it a bit before and after the 
multiplication.

Many FPGAs have 18x18 bit multipliers with a 36bit result. To use that, 
all calculations should be made with max 18bits:

Your 32bit integer value can only use 22 bits to fit in a byte when 
divided by 14800.
So you can ignore the higher 10 bits, and with such a high divisor you 
can also ignore some lower end bits to make it fit into 18bits.

With 18.18 bit fixedpoint in Verilog:
wire [35:0] scaleVal = count[21:4] * 18'd145100;  // * 0.55351 = 2^15/14800
assign byteVal = scaleVal >> 11;                  // >>(18-15+8)

Author: Andy (Guest)
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Sorry I mixed up the shifts from different tries, this should be 
correct:
wire [35:0] scaleVal = count[21:4] * 18'd145100;  // * 0.55351 = 2^13/14800
assign byteVal = scaleVal >> 9;                   // >>(18-13-4+8)

If you can tolerate some error and have no multipliers:
assign byteVal = (count>>14) + (count>>17);

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