Is there a tool that tells which variable is assigned more then it size(no. of bits). VHDL will throw an error but verilog does not throw an error. It just truncates the extra bits assigned to the variable. Please Help!
Synthesis Size Mismatch Warning Lint Tools
In Verilog the bitsize of the destination (on the left) dictate the size that is used for the whole expression. All the nets on the right side of the expression get truncated or expandend to that bitsize automatically. That's one of the big advantages of Verilog over VHDL (for me).
An implicit truncation is bad coding style and will lead to synthesis/lint warnings. An implicit expansion can be discussed.
Agreed, there is normally something wrong if it gets truncated.