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Forum: FPGA, VHDL & Verilog Controlling the tasks


Author: Sushma K. (Company: None) (digital_treasure)
Posted on:

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Hello,

I have a strange question with regards to task control in verilog test 
bench, so please bear with my attempt to trying to keep it to a simple 
form.

I have a task flow inside a file, for which I am not permitted to change 
anything. For example;
   1) File: Faults
  task examine;
  begin
  task a();
  task b();
  end

  the explanations for task a and b are also inside the file-Fault for 
which I am not permitted to make any changes.

However I am using the above task in my test case
  2) File : Testcase_1
   task xyz;
   task examine;
   task hml; etc..

however there is a problem with task a. when task-a runs, there is a 
variable inside that task which is changing wrongly and I have to force 
the variable to follow the right formula somewhere else and correct it 
without doing the task correction in the Faults file.

I have access to  another file called as File: utility where I can write 
the correct formula to force the variable to follow the new formula, get 
changed and then continue executing with task b and so on in my test 
case and produce the results.


But I dont know how can I stop task a in the middle and then change the 
variable(force it follow a new formula and get the right value) and then 
continue with task b and so on. Can anybody help me with this???


i am happy to provide additional info if required. Thanks in advance

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