EmbDev.net

Forum: FPGA, VHDL & Verilog VIVADO IP integration


VIVADO IP integration
Author: Elico C. (Company: WS) (elico)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
Hi all

Can I do an VHDL based IP and reuse it by integratig it in a schematic 
based design ( just getes withouut vhdl) and compile it all together and 
simulate it ?

Thanks

Elico

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.