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Forum: FPGA, VHDL & Verilog IP with axi-stream slave and axi4-full master interface


Author: zyed (Guest)
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Dear all,
I am developing a custom AXI IP using vivado. it  has axi-stream slave
and  axi4-full master interface. my goal is to connect the master
interface to zed board HP0 (axi3 slave interface). Since the input is
the input and output axi standards are different i dont  know how to map
the input AXI stream signal to AXI4 ful master interface. I tried
earlier where both I/O were stream interface where i simply mapped input
to output and it worked fine. any suggestion would be really helpful to
proceed. Thanks

Author: Klakx (Guest)
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you need to look for a AXIS-AXI_Memory-Mapped DMA. In Vivado it is 
called Datamover. AXI4-MM is a complex bus technology, where axi-stream 
is just a simple data stream. You need logic&fsm to forward your stream 
on adresses.

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