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Forum: FPGA, VHDL & Verilog IPs in XILINX ise


von Elico C. (Company: WS) (elico)


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Hi all

Can I design an IP that is composed just by VHDL code and integrate it 
in
ISE tool for further usage in other projects?

Elico

von Make it possible (Guest)


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At least, I can.

von Elico C. (Company: WS) (elico)


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Thanks

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