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Forum: FPGA, VHDL & Verilog VIVADO +SCHEMATICS + VHDL


Author: Elico C. (Company: WS) (elico)
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Hi all
is it possible to do a design in VIVADO based on self made schematics  + 
VIVADO IPs + some VHDL code +some vhdl based testbench that will help 
simulation of the whole design ?

Author: Cle (Guest)
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Schematic is a very ambiguous term, what do you mean with this term?

The rest ist possible. As nearly everything is possible if you describe 
is as unprecise as possible.

Author: Elico C. (Company: WS) (elico)
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Schematics is a design based on gates only like or nand , counter 
without any vhdl jast the testbench used to simuate that gates based 
design.

Elico

Author: Cle (Guest)
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But how will you tell your software what kind of nand and other blocks 
you want to use? What is your design entry method? I would say no as 
there is no way in Vivado to entry a design in any form of schematic 
(and as is doesn't make sense). And of couse you could misuse block 
designs, but that creates more problems and makes it harder than just 
transfering the schematics to a HDL of your choice.

And by the way, building designs based on NANDs isnt very useful in the 
FPGA design area as your base building blocks differ from the blocks you 
would use in another IC design flow.

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