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Forum: FPGA, VHDL & Verilog Logical case equality and inequality operators utilizing No of LUTs


Author: Lakshita J. (lakshita)
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Hello

I am working on point addition algorithm for ecc implementation,the 
verilog code is having logical case equality and inequality operators 
utilizing 238 % LUTs.
I am targeting Nexys 4 ddr FPGA board

In verilog code,
line no 33-
wire addinf = ((x2 === zreg && y2 === zreg) && (x1 !== zreg && y1 !== 
zreg)) || ((x1 === zreg && y1 === zreg) && (x2 !== zreg && y2 !== 
zreg));

When these operators are replaced with logical equality and logical 
inequality(!= and ==)operators then the no of luts decreases but it 
affects simulation results

wire addinf = ((x2 == zreg && y2 == zreg) && (x1 != zreg && y1 != zreg)) 
|| ((x1 == zreg && y1 == zreg) && (x2 != zreg && y2 != zreg));

I have attached the verilog code and the screenshot of 2 project summary

Any suggestions to this problem?

Author: Guest (Guest)
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You are STILL using all those modulo operators. Can't you just find an 
algorithm that's actually suited for implementation? There has to be 
some way to do this more efficiently.

Other than that, changing the addinf line likely results in a constant 
value for addinf which leads xst to synthesize away most of your code. 
Not sure why though, the === and !== operators don't make any sense for 
implementation anyways.

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