I am working on point addition algorithm for ecc implementation,the
verilog code is having logical case equality and inequality operators
utilizing 238 % LUTs.
I am targeting Nexys 4 ddr FPGA board
In verilog code,
line no 33-
wire addinf = ((x2 === zreg && y2 === zreg) && (x1 !== zreg && y1 !==
zreg)) || ((x1 === zreg && y1 === zreg) && (x2 !== zreg && y2 !==
When these operators are replaced with logical equality and logical
inequality(!= and ==)operators then the no of luts decreases but it
affects simulation results
wire addinf = ((x2 == zreg && y2 == zreg) && (x1 != zreg && y1 != zreg))
|| ((x1 == zreg && y1 == zreg) && (x2 != zreg && y2 != zreg));
I have attached the verilog code and the screenshot of 2 project summary
Any suggestions to this problem?