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Forum: µC & Digital Electronics AVR USI TWI master/slave config


AVR USI TWI master/slave config
von Christoph L. (lehrlii)

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Hi folks,

I'm currently developing a sensor framework based on the TWI bus and I 
use ATtiny85's as sensor nodes.
I want them to be able to communicate as TWI master, therefore I wanted 
to implement the USI in TWI mode with Timer0 as clock.

So my questions are:
1. Do I have to use OCR0A or OCR0A?
2. When using Timer0, do I have to generate the clock manually or is it 
done by the HW?
3. For bus arbitration I would need to detect if the bus is in use. Is 
there a efficient way the detect stop conditions?

Unfortunately not even AVR believes in the USI interface and the whole 
application notes depend on polling and the ATtiny85's datasheet is very 
vague on this topic.

Thanks in advance.

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Re: AVR USI TWI master/slave config
von Hermann (Guest)

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You intend to make the I2C-communication by yourself? In this connection 
I can't help.
I use Bascom and there is a library for master and slave which use the 
USI-HW. I suppose a simular library is available in C. So you have 
nothing to do with bits, clock and timer.
This is quite simple. To practice I have made a master which reads and 
writes an EEPROM. And then I made a slave which emulates this EEPROM. 
The only problem: the slave library costs about 14€ for all SW and HW 
solutions.
If you are interested I can post the short source code.

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