I have a data source signal that transitions high on the positive edge of its clock when it has data ready to be written. I also have ram memory that expects it's write request signal to transition on the negative edge of the clock (and stay high until the following negative edge of the clock). If I try driving the wr_req directly from the data source then both the clock and wr_req transition at the same time and the memory doesn't get the data. How can I delay the write pulse such that it goes high (for one cycle) starting on the next negative edge of the clock?
output <= not input;
Just inverting would make the normally low (active high) write signal always high, causing many writes to the memory.
If I understand your problem right, you want to drive a signal on the falling clock edge. So just use the falling_edge (negedge in verilog). If you don't mix it up in one process, you can create FFs which react on either falling or rising clock edge (but not on both in most todays FPGAs technologies).
if (falling_edge(clk)) then
wr_req_to_ram_neg_edge <= wr_req_from_src_pos_edge;
I assume the data also has to be stable from negedge to negedge, so you also have to sync the data on the negedge.
Thanks! that worked great.. I think I was making it too complicated!