EmbDev.net

Forum: FPGA, VHDL & Verilog Project Design


Author: Dayana (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hi everyone.
 
My project design involve Systolic Array. Systolic Array is build up of 
several Processing Element (PE) as shown in the Figure 1 below.
As shown in the Figure 1,  each PE holds one Query Character.
 
Thus, in my design as shown in Figure 2, the 3-bit Query Character (QC) 
i/p for PE is connected to QueSec i/p at the top module so that all the 
query characters are loaded in each PE through QueSec i/p in parallel. 
However, due to limited i/o in FPGA, the actual no. of PEs cant be 
generated, because of the big size i/p.   
 
To overcome the i/o issue, I have to change QueSec i/p size to 3-bit, 
not as shown in Figure 2. But by using this size i can only see that the 
data will be loaded serially not in parralle.
 
Can anyone give me some idea, to use 3-bit QueSec i/p size and the data 
in parallry insert in each PE?
 
Thank you very much for helping me.

Author: Theor (Guest)
Posted on:

Rate this post
0 useful
not useful
Hm.

You wrote: "But by using this size i can only see that the data will be 
loaded serially not in parralle."

Is'nt that enough for a solution?

You see, as I understand that sentence, that data will be loaded 
serially - so why dont do exactly that?


But I must add, that I may have missed the point.

You later ask: "... and the data in parallry insert in each PE"

And I nearly instantly think like: "Uh. Fine. You put out in parallel 
what you previously had input serial". Whats the problem?"

But you may not be aware, that a sequence of flip-flops, feeded serial 
with data and a clock line, may even so output its content in parallel.

Does that help you any further?

Author: Dayana (Guest)
Posted on:

Rate this post
0 useful
not useful
> You wrote: "But by using this size i can only see that the data will be
> loaded serially not in parralle."
>
> Is'nt that enough for a solution?

I can do that. However, I didnt know how to control the input as only 1 
data will be loaded in each PE and with different data.


> You see, as I understand that sentence, that data will be loaded
> serially - so why dont do exactly that?
>
> But I must add, that I may have missed the point.
>
> You later ask: "... and the data in parallry insert in each PE"
>
> And I nearly instantly think like: "Uh. Fine. You put out in parallel
> what you previously had input serial". Whats the problem?"
>
> But you may not be aware, that a sequence of flip-flops, feeded serial
> with data and a clock line, may even so output its content in parallel.
>
> Does that help you any further?

If I use SIPO , it will have mutiple 3-bit o/p which will also will sud 
up all the I/O in FPGA.

Author: Theor (Guest)
Posted on:

Rate this post
0 useful
not useful
Hm. Still a bit odd.

It sounds, that you are a learner (i.e. a student).


If the fpga hast no enough inputs to get the data in parallel at once, 
than - as I told and as you yourself had the very thought - get it in 
sequential.

I think we got that straight so far.


You replied in two regards:

1. "...how to control the input as only 1 data will be loaded in each PE 
and with different data."

True: Thats the very thing with serial to parallel conversion. Please 
look at some descriptions of serial to parallel converters in the 
textbooks or the internet. These are basic mechanisms.


2. "... it will have mutiple 3-bit o/p which will also will sud up all 
the I/O in FPGA."

That would be true, if you would implement the 
serial-to-parallel-converter outside of the FPGA in question. But for 
what reason would you do it that way, if your first objective is to 
reduce the number of inputs? Why not using the FPGA not only for the 
whatever it does but for the serial-to-parallel conversion also ?


Please try to use and think of terms carefully

Inside the FPGA there are not input/outputs in the same sense as at the 
border between the outside (the world, lab or classroom) and the inside 
of an FPGA (the silicon chip). So you will not necessarily use all the 
I/O in an FPGA, but that of an FPGA - in case you place the 
serial-to-parallel-converter outside the FPGA. And as I said - why not?

Author: Dayana (Guest)
Posted on:

Rate this post
0 useful
not useful
Yes i'm a student.  hahaha

Thank you for your time and explanation.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig