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Forum: FPGA, VHDL & Verilog Mapping block RAMs to specific address space


Author: Sajjad Hussain (Company: KIT) (engg_sajjad)
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I am trying to load my program to a Block RAM using Data2mem, after the 
bitfile is generated. Here are the steps:

I have generated a BLOCK RAM as single port ROM with 32 bit-width and 
16384 bit-depth.
Then translated the design without any BMM file and looked at the 
PlanAhead tool to see which BRAM are used and which ramloop is assigned. 
There are 15 ramloop lines. There are 14 PRIM36 primitives and 1 PRIM18 
primitive as shown below:
BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP  **(RAMB18)**

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP 
**(RAMB36_EXP)**

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  (RAMB36_EXP)

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  (RAMB36_EXP)

⋮⋮
BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  (RAMB36_EXP)

I wrote the following .BMM file for address the ROM from 0x0000 to 
0xFFFF. and add it to the xilinx project.
ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff]
BUS_BLOCK

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP  [31:0];
    END_BUS_BLOCK;
    BUS_BLOCK

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  [31:0];
    END_BUS_BLOCK;
    BUS_BLOCK

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  [31:0];
    END_BUS_BLOCK;
    BUS_BLOCK

BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  [31:0];
    END_BUS_BLOCK;
    BUS_BLOCK

⋮⋮
BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/val 
id.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  [31:0];
    END_BUS_BLOCK;
    END_ADDRESS_SPACE;

But when I tried to compile it again it gives me the error:
ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE 
'pr_mem1'.

Can you please help me out where the error is occurring? Is ramloop[xx] 
correctly used?

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