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Forum: FPGA, VHDL & Verilog VHDL if construct assistance


Author: Rejoy Roy Mathews (Guest)
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Port w, x, y and z are defined as STD_LOGIC.

In my 'if' construct I use the below condition
if((not w) and (not x) and (not y) and (not z)) then
--Do something

instead of the actual proper syntax as below.

 if( w = '0' and x = '0' and y = '0' and z = '0') then
--Do something

The former implementation fails and returns the below error
type error near w ; current type std_logic; expected type boolean

I understand that VHDL is a strongly typed language and hence it returns 
this error.

However consider a second case i.e. if i had to do an assignment c <= 
not a (Where a and c are of type STD_LOGIC), the execution will proceed 
without an error.

I am looking for a proper reason to give my students as to why the 'if' 
construct fails but the assignment succeeds in VHDL.

Thank you.

Author: Lothar Miller (lkmiller) (Moderator)
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The "not" operator for std_logic gives a std_logic in return.

A "=" operator gives a boolean in return.

A "and" operator expects boolean operands.

With that information the behavior becomes clear.

: Edited by Moderator
Author: Rejoy Roy Mathews (Guest)
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Thank you Lothar Miller for the clear and succinct explanation.

Author: Markus F. (mfro)
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VHDL 2008 relaxes the overly strict behaviour and allows std_logic in 
boolean context within if statements.

This can even be enforced with the '??'-Operator where this behaviour 
would lead to ambiguity.

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