Design algorithmic state machine comprising of controller and datapath 
implemented in RTL based model, which can find how many times a virus 
pattern equal to 1011 occurs in a data file (data files are to be 
uploaded on the group).
a) Draw structural block diagram of controller and datapath along with 
signals.
b) Draw ASMD chart of the state machine.
c) Give RTL level verilog description of controller (FSM) and datapath.
d) Design integrated test bench for the machine and verify your design 
in simulated mode on provided test data files.
e) Verify working of the design on FPGA based development kit in the lab 
on the given test data files.
Example for pattern matching: In pattern matching, a sequence is scanned 
bit by bit and once a required pattern is found, the scan restarts from 
the next bit. For example, we have 11011101011 in the data file, the 
scanning process start from the left, we have 11 at that start (first 
and second bit) that is different from the virus pattern (1011), since 
it’s a mismatch, the scan starts form the second bit. Upon restarting 
the scan from second bit, we have found that the virus pattern exists in 
the next four bits, so the counter is incremented to one and the scan 
restarts form sixth bit and this process continues until the end of 
file.
Input phase: Data files that contains large strings of binary sequence; 
is downloaded, either in the flash or in FPGA memory. Find it by you own 
that how we do it on FPGA.


Output phase: A Reset button (pushbutton BTN0) that resets the value of 
counter, and a Go button (pushbutton BTN1) that displays the counter 
value (number of times the virus pattern 1011 exists in a data file) on 
both seven segment displays (in decimal form) and on 8 LEDs (in binary 
form). Considering the above example, the seven segment should display 1 
as well as the LED should display the binary form of 1.

Is this code is valid for part (C) and i have bit stream in data file 
how i can store this fie in my test bench
  CoDe

                                                                    VERILOG 
CODE
module bat
#(parameter N=1, M=12 )
(input wire a,
    input wire clk,
    input wire reset,
    output wire y, z,
   output reg [2**M:0] c,c_new  );
   localparam [1:0]     s0 = 2'b00,
                                     s1 = 2'b01,
            s2 = 2'b10,
            s3 = 2'b11;
reg [1:0] state_reg, next_state;
reg  [N-1:0] b_reg[2**M-1:0];
reg [2**M-1:0] i;
  //State Register
  always @ (posedge clk, posedge reset)
  if (reset)
  state_reg <= s0;
  else
  state_reg <= next_state;
  //Next Logic
  always @ (*)
  begin
  case (state_reg)


s0 :
begin
 if (b_reg[i]==1)
next_state = s1;
else
b_reg[i] = i+1;
next_state =s0;
end

s1 :
begin
if(b_reg[i]==0)
next_state = s2;
else
next_state =s0;
 b_reg[i] = b_reg[i]+1;
end

s2 :
begin
 if(b_reg[i]==1)
next_state = s3;
else
next_state =s0;
b_reg[i] =b_reg[1]+1;
end

s3 :
begin
 if(b_reg[i]==1)
next_state = s0;
else
b_reg[i] =b_reg[i]+1;
next_state =s0;
assign c_new = c+1;
end

default : next_state = s0;
endcase
end
             //Output Logic
 assign y = (state_reg==s3) ? 1'b1 : 1'b0;                    // y is 
for resetting value of counter
 assign z= c_new; 
// z is for total counter value
endmodule
                                                            TEST MODULE
module t;
  reg a;
  reg clk;
  reg reset;
  wire y;
  bat uut (
    .a(a),
    .clk(clk),
    .reset(reset),
    .y(y));
always
  begin
clk=0;
 #100;
 clk=1;
 #100;
 end
  initial begin
reset = 0;
  a = 1;
  #100;
  reset = 1;
  a = 0;
  #100;
  end
  endmodule