# Forum: FPGA, VHDL & Verilog verilog if else to casex

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Replace this if-then statement with a casex statement

reg A, B, C, D, E, F, G, H;
always@(*)
if (A) H = F & G;
else if (B) H = F | G;
else if (C) H = F ^ G;
else H = D & E;

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We do not do your homework! Show what you have and ask questions, so we
can help.

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Please see the attached file.
That is what i think , i dont know the correct use of casex statement
and the parameters to be given inside casex()
please help me out

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 1 reg A, B, C, D, E, F, G, H;  2 always@(*)  3 casex({A,B,C})  4  3'b1xx:H = F & G;  5  3'b01x:H = F | G;  6  3'b001:H = F ^ G;  7  3'b000:H = D & E; 

think in sets.
The first if only concerns the A, the others don't matter.
the second if is inside the else clause to the first if so A==0 and
B==1. c
does not matter. the third if is in the else clause to the previous
statements, so A==0 B==0 and C==1. the last else selects the only
leftover condition. A==0 B==0 C==0.

A  B  C
0  0  0  ->what's left for the else
0  0  1  ->third if
0  1  0  \->second if
0  1  1  /
1  0  0  \
1  0  1   |
1  1  0   |->first if
1  1  1  /

• $formula (LaTeX syntax)$