I am running Libero V11.8 with a Proasic3 A3P060-100VQFP attached to a
10MHz clock.
I am trying to get my first ever sketch running, it's extremely simple.
One input CLK, and 4 outputs LED (3 downto 0), the code is below, it
seems to check out fine.
It synthesizes with no problem, but then I go to set the I/O constraints
and run into a big problem.
I click on "Create/Edit I/O Constraints", it brings up the Designer and
the MultiView Navigator (see attached screenshot), it lists all the
outputs LED[0-3], but it doesn't list the CLK input. Because it doesn't
list the CLK input I have no way of assigning it the onboard clock and
the program doesn't do anything.
How do I get it to allow me to attach the the input? I tried renaming
CLK and even adding other inputs, but none of them appear in the
constraints editor.
I'm sure there is something simple I am missing, if anyone can point it
out I'd be grateful.
Thanks,
Josh
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: LED.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::ProASIC3> <Die::A3P060> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity LED is
port (
CLK : in std_logic;
LED : out std_logic_vector (3 downto 0)
);
end LED;
architecture architecture_LED of LED is
signal pulse : std_logic := '0';
signal count : integer range 0 to 9999999 := 0;
begin
process(CLK)
begin
if (CLK' event and CLK = '1') then
if count = 9999999 then
count <= 0;
pulse <= not pulse;
else
count <= count + 1;
end if;
end if;
end process;
LED (3 downto 0) <= (others => pulse);
end architecture_LED;
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