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Forum: FPGA, VHDL & Verilog Libero V11.8 troubleshooting


Libero V11.8 troubleshooting
von Josh R. (Company: ALE CO Ltd) (jrodenba)

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I am running Libero V11.8 with a Proasic3 A3P060-100VQFP attached to a 
10MHz clock.
I am trying to get my first ever sketch running, it's extremely simple. 
One input CLK, and 4 outputs LED (3 downto 0), the code is below, it 
seems to check out fine.

It synthesizes with no problem, but then I go to set the I/O constraints 
and run into a big problem.
I click on "Create/Edit I/O Constraints", it brings up the Designer and 
the MultiView Navigator (see attached screenshot), it lists all the 
outputs LED[0-3], but it doesn't list the CLK input.  Because it doesn't 
list the CLK input I have no way of assigning it the onboard clock and 
the program doesn't do anything.

How do I get it to allow me to attach the the input?  I tried renaming 
CLK and even adding other inputs, but none of them appear in the 
constraints editor.
I'm sure there is something simple I am missing, if anyone can point it 
out I'd be grateful.
Thanks,
Josh

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--------------------------------------------------------------------------------

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-- Company: <Name>

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--

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-- File: LED.vhd

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-- File history:

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--      <Revision number>: <Date>: <Comments>

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--      <Revision number>: <Date>: <Comments>

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--      <Revision number>: <Date>: <Comments>

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--

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-- Description: 

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--

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-- <Description here>

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--

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-- Targeted device: <Family::ProASIC3> <Die::A3P060> <Package::100 VQFP>

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-- Author: <Name>

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--

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--------------------------------------------------------------------------------

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library IEEE;

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use IEEE.std_logic_1164.all;

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entity LED is

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port (

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    CLK : in std_logic;

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    LED : out std_logic_vector (3 downto 0)

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);

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end LED;

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architecture architecture_LED of LED is

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    signal pulse : std_logic := '0';

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    signal count : integer range 0 to 9999999 := 0;

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begin

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   process(CLK)

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    begin

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        if (CLK' event and CLK = '1') then

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            if count = 9999999 then

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                count <= 0;

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                pulse <= not pulse;

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            else

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                count <= count + 1;

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            end if;

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        end if;

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    end process;

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    LED (3 downto 0) <= (others => pulse); 

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end architecture_LED;


  


  




  

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    Re: Libero V11.8 troubleshooting
  


  

    

      von
      
        Josh R.
            (Company: ALE CO Ltd)
        (jrodenba)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Well...
I started the project over from scratch and when I went to assign the 
I/O pins, CLK showed up and I was able to assign it to the onboard 
clock.
The LEDs blink now.  Still no clue as to what I did wrong the first 
time, hopefully the issue won't come up again.

  


  




  

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