Forum: FPGA, VHDL & Verilog Connecting Several Modules and a USB

von Christopher B. (Company: UMASS) (brissettecj)

Rate this post
0 useful
not useful
Hello! I am trying to research side channel attacks on a 32-bit 
architecture of AES and my very limited knowledge of circuits and of 
Verilog is biting me in the behind.

I am trying to research some AES side channel attacks on an Artix-7 FPGA 
via this board: https://wiki.newae.com/CW305_Artix_FPGA_Target

I am trying to put this version of AES on it: 

Specifically I want to use the USB / Register interface here: 
(Because it connects to the FPGA and I know it works)

More specifically the files "cw305_top.v", "usb_module.v", and 
"registers.v". Again, here: 

And I want to replace the 128-bit architecture with the 32-bit one from 
above, all files here: 
https://github.com/secworks/aes/tree/master/src/rtl (Most notably 

Essentially I just want to get the 32-bit aes_core into the place of the 
128-bit aes_core from above, where by 32-bit I mean something similar to 

Thank you for any guidance or help in this. I am just so lost.

Thanks in advance,


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.