Hello! I am trying to research side channel attacks on a 32-bit architecture of AES and my very limited knowledge of circuits and of Verilog is biting me in the behind. I am trying to research some AES side channel attacks on an Artix-7 FPGA via this board: https://wiki.newae.com/CW305_Artix_FPGA_Target I am trying to put this version of AES on it: https://github.com/secworks/aes Specifically I want to use the USB / Register interface here: https://github.com/newaetech/chipwhisperer/tree/master/hardware/victims/cw305_artixtarget/fpga (Because it connects to the FPGA and I know it works) More specifically the files "cw305_top.v", "usb_module.v", and "registers.v". Again, here: https://github.com/newaetech/chipwhisperer/tree/master/hardware/victims/cw305_artixtarget/fpga/common And I want to replace the 128-bit architecture with the 32-bit one from above, all files here: https://github.com/secworks/aes/tree/master/src/rtl (Most notably "aes_core.v") Essentially I just want to get the 32-bit aes_core into the place of the 128-bit aes_core from above, where by 32-bit I mean something similar to this: https://www.researchgate.net/publication/254073694_A_Compact_32-bit_Architecture_for_an_AES_System Thank you for any guidance or help in this. I am just so lost. Thanks in advance, Chris