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Forum: FPGA, VHDL & Verilog FPGA Tasks to do


Author: Jnine (Guest)
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Hi!

I have some tasks to do but I stuck. Can you help me please?

https://docs.google.com/document/d/1qZBdjqS52crgaW...

Kind regards

Author: aaa (Guest)
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for sure.

Whats your Problem?

Author: Jnine (Guest)
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Task 1 has two questions.

1. How would a DCM_SP block react if the BCLK loses its signal level?
I dont know the answer through too less experience. But I guess MCLK 
would lose its signal level as well?

2. Solution for an automatic clock recovery?
Maybe a second DCM?

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