EmbDev.net

Forum: FPGA, VHDL & Verilog FSM: a state gets latched


von Daniel (Guest)


Attached files:

Rate this post
useful
not useful
Hi,
i am running a state machine.
Simulation shows everything is OK.
Real life implementation is showing otherwise.
I keep track of the states using on board LEDS showing the current FSM 
state.
The problem is that at a certain point (couldn't figure out if there is 
a specific sequence except that its not from the WAIT STATE), the FSM 
transfer to the INIT STATE and gets stuck there until i do a POWER 
reset, which is weird by itself because there is no such transition 
possible, as i made sure that the reset_L signal is not LOW.
and gets stuck at that state, even though that even if such a transfer 
should happen, an immediate transfer to WAIT state should happen but 
doesn't.


I cant find the reason and the solution, please help...
THE CODE IS ATTACHED

von Viktor B. (coldlogic)


Rate this post
useful
not useful
Hi Daniel,
it seems that you are getting impossible states. Are your signals which 
drive the states properly synchronized? It may lead to such problems.

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.