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Forum: FPGA, VHDL & Verilog FSM: a state gets latched


FSM: a state gets latched
von Daniel (Guest)

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Hi,
i am running a state machine.
Simulation shows everything is OK.
Real life implementation is showing otherwise.
I keep track of the states using on board LEDS showing the current FSM 
state.
The problem is that at a certain point (couldn't figure out if there is 
a specific sequence except that its not from the WAIT STATE), the FSM 
transfer to the INIT STATE and gets stuck there until i do a POWER 
reset, which is weird by itself because there is no such transition 
possible, as i made sure that the reset_L signal is not LOW.
and gets stuck at that state, even though that even if such a transfer 
should happen, an immediate transfer to WAIT state should happen but 
doesn't.


I cant find the reason and the solution, please help...
THE CODE IS ATTACHED

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Re: FSM: a state gets latched
von Viktor B. (coldlogic)

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Hi Daniel,
it seems that you are getting impossible states. Are your signals which 
drive the states properly synchronized? It may lead to such problems.

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