# Forum: FPGA, VHDL & Verilog Viterbi Decoder

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I'm sorry if I have broken the rules by making this a general post. I am
attempting to create a decoder for convolution-encoded parity arriving,
and needing to be processed, at a rate of 100Mbits/s, this being my
preferred clock frequency for the Zynq 7045 SOC I am using for the job.
I have elected to make my first attempt a register exchange engine,
bearing in mind that some academics have proposed methods by which the
physical exchange of registers might be avoided.

My question, however is related to whether this device should operate on
blocks, or in a continuous mode, in case there is any statistical merit
in operating the decoder in a manner in which it outputs a bit every
clock, based on a path metric obtained by subtracting the branch metrics
associated with the beginning of a path, and adding those calculated
most recently. The comparison of path metrics for each state being
performed every clock cycle. Such a comparison, in the case of my
application, being of 64 words, probably requiring some degree of
pipelining, necessary information needing to be stored for the depth
thereof.

Given that it might be determined that L state transitions are needed to
compute a reliable estimate of the last L uncoded information bits, and
that the method I am speculating would discard all but the earliest of
these, I have doubts regarding its validity, a problem, for me, being
that, with a moving trellis of finite length L, initial conditions are
inherited, rather than assumed, it seeming to me that they should be
reset at eack clock tick, and costs recalculated over all states
(columns) in the trellis. The latter making the implementation demanding
of resources probably unavailable. My decision length, L, is 128, and
there are, as mentioned, 64 states.

The large decision length is determined by the considerable puncturing
of the 4-bit mother parity code required by the customer. Code rates
from 8/9 to 1/4 need to be supported.

Any help would be appreciated.
Best regards
Julian

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