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Forum: FPGA, VHDL & Verilog Wrong syntax near


Wrong syntax near
von Cergey C. (cossack5)

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Hi,
Can someone help as to what's wrong with the following line of code:
  signal delay_needed : std_logic_vector(31 downto 0):= 
"0000000000000000000000000010100";

Full Code:

1
library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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4
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use ieee.numeric_std.all;

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use IEEE.std_logic_unsigned.all;

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use IEEE.numeric_std.all;

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use IEEE.std_logic_arith.all;

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entity delay is

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  port (clk : in std_logic; 

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--delay to be generated.

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        a : in std_logic_vector(31 downto 0);   

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--this is a pulse to notify that time interval equal to delay is over.

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        flag : out std_logic 

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    );

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end delay;

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architecture Behavioral of delay is

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    signal count :integer:=0;

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    begin

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    process(clk)

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        begin

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        if(clk'event and clk='1') then

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        count <= count +1;   --increment counter.

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        end if;

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        --see whether counter value is reached,if yes set the flag.

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        if(count = conv_integer(a)) then 

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        count <= 0;

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        flag <='1';

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        else

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        flag <='0';

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        end if;

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    end process;

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end Behavioral;

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use ieee.numeric_std.all;

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use IEEE.std_logic_unsigned.all;

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use IEEE.numeric_std.all;

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use IEEE.std_logic_arith.all;

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entity device is

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    Port ( 

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        CLK : IN STD_LOGIC;

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         SATN : in INTEGER;

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         VALUE : OUT INTEGER

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           );

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end device;

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architecture Behavioral of device is

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    signal flag : std_logic :='0';

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    signal delay_needed : std_logic_vector(31 downto 0):= "0000000000000000000000000010100"; 

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   inst_delay : test port map(clk,delay_needed,flag);

61
    

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    type initvec is array (0 to 1022) of integer;

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    signal g1 : initvec:=(others=>0);

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    signal g2 : initvec:=(others=>0);

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    signal ca : initvec:=(others=>0);

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        signal tmp_shift : initvec:=(others=>0);

67
        

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        type neg is array (0 to 9) of integer;

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        signal reg : neg:=(others=>-1);

70
    

71
    

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    type prns is array (31 downto 0) of integer;

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    signal Prn   : prns:=(5,6,7,8,17,18,139,140,141,251,252,254,255,256,257,258,

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  469,470,471,472,473,474,509,512,513,514,515,516,859,860,

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    861,862);

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begin

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process(clk)

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variable saveBit :integer;

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variable count : integer;

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begin

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if(clk'event and clk='1') then

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      for I in 0 to 1022 loop

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      g1(I) <= reg(9);

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      saveBit := reg(2)*reg(9);

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      reg(1 to 9) <= reg(0 to 8);

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      reg(1) <= saveBit;

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    end loop;

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    reg <=(others=>-1);

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    for J in 0 to 1022 loop

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      g2(J) <= reg(9);

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      saveBit := reg(1)*reg(2)*reg(5)*reg(7)*reg(8)*reg(9);

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      reg(1 to 9) <= reg(0 to 8);

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      reg(1) <= saveBit;

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    end loop;

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    tmp_shift (0 to SATN) <= g2(1022-SATN to 1022); 

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    g2(SATN+1 to 1022) <= g2(0 to 1022-SATN);

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    g2(0 to SATN) <= tmp_shift (0 to SATN);

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    if (flag'event and flag='1')

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       then

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         if (count < 1023) then

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              VALUE <= -1*(g1(count)*g2(count));

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           end if;      

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        end if;

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      end if;

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end process;

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end Behavioral;


  


  



  

  
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    Re: Wrong syntax near
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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With your code I get this:
1
Size mismatch.  String literal "0000000000000000000000000010100"

2
is of size 31 but is expected to be of size 32.


After correction i get:
1
parse error, unexpected IDENTIFIER

This is for:
inst_delay : test port map(clk,delay_needed,flag);
But I cannot find any component named test. Should it be delay?

Additionaly the architecture header is not for instantiation, you must 
declare the component there. Instantiation is done later in the 
architectures body:
1
:

2
:

3
architecture Behavioral of device is

4
    signal flag : std_logic :='0';

5
    signal delay_needed : std_logic_vector(31 downto 0):= "00000000000000000000000000010100"; 

6
    

7
    type initvec is array (0 to 1022) of integer;

8
    signal g1 : initvec:=(others=>0);

9
    signal g2 : initvec:=(others=>0);

10
    signal ca : initvec:=(others=>0);

11
        signal tmp_shift : initvec:=(others=>0);

12
        

13
        type neg is array (0 to 9) of integer;

14
        signal reg : neg:=(others=>-1);

15
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component delay is

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  port (clk : in std_logic; 

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        a : in std_logic_vector(31 downto 0);   

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        flag : out std_logic 

20
    );

21
end component;    

22
23
    

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    type prns is array (31 downto 0) of integer;

25
    signal Prn   : prns:=(5,6,7,8,17,18,139,140,141,251,252,254,255,256,257,258,

26
  469,470,471,472,473,474,509,512,513,514,515,516,859,860,

27
    861,862);

28
begin

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   inst_delay : delay port map(clk,delay_needed,flag);

30
:

31
:


After fixing that you will get some errors further on you have to dig 
out...

And then this here:
1
use ieee.numeric_std.all;

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use IEEE.std_logic_unsigned.all;

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use IEEE.numeric_std.all;           -- second time: much is more?

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use IEEE.std_logic_arith.all;

Never ever use the numeric_std and the std_logic_unsigned together. You 
may encounter some strange error messages due to double definitions of 
data types.

All in all: VHDL is not a programming language. Instead it is a 
description language. So you should have a picture of the hardware you 
want to describe (at least in mind). As far as I see you are 
programming. This is very obviuos here:
type initvec is array (0 to 1022) of integer;
That becomes a huge distributed RAM, eating up lots of FPGA ressources.

BTW: pleas use the [vhdl] tags around VHDL code.

  


  



  

  
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