EmbDev.net

Forum: FPGA, VHDL & Verilog Xilinx's RAM


Author: Joey Weyland (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello, im new on this forum.
Im trying to learn how to use a extern DDR2 RAM that my Virtex 5 have. I 
honestly dont know the step by step. I do this to learn how to use the 
FPGA in order to gaining experience for a future proyect. The most 
difficult module that i used was the Display and works fine.
Im using ISE 14.7
With the DDR2 RAM the only thing i did was creating the file that Core 
Generator Tool provides after the first configuration.
I had a problem there: i couldnt assign all the ports but i was able to 
create the file anyway. Now i'm not shure what to do next. I'd apreciate 
any help that someone can provide or some tip to follow.

Sorry but im a little lost in this subject.

I have a Virtex 5, XC5VLX50T.

Thank you!

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig