Implementing Recast block in FPGA.

Guest #5021293
Rate this post
• ▲ useful
▼ not useful
Hello all!

 I'm trying code a lỉbrary equal HDL(verilog language). But I don't 
understand how can I do it. Please help me.

  Name and the use this block : "Recast: The Recast block provides value 
based on the requested data type cast at  the output, maintaining the 
same bits as provided at the input".

 Thanks.

 Japa
Guest #5022188
Rate this post
• ▲ useful
▼ not useful
I see sth like:
"The Recast block provides value based on the requested data type cast 
at  the output, maintaining the same bits as provided at the input" in 
property of this block, I have to use it to implement in FPGA, with 
Xilinx, hope anyone help me to to solve this problem.

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.