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Forum: FPGA, VHDL & Verilog ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for


Author: TienNguyen (Guest)
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I have a code at below. I don't know how can i use the loop for??? Pls, 
help me!!! (Verilog language, this code in ISE Design Suite 14.4).
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for 
for

   always @ (dataIn or index)
     begin
        for(i = 0;  i <= index; i = i + 1)
          dataOut[i] = dataIn[i];
        for(i = index+1;  i < size; i = i + 1)
          dataOut[i] = 1'b0;
     end

Author: Duke Scarring (Guest)
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try:
always @ (dataIn or index)
     begin

        for(i = 0;  i < size; i = i + 1)
          if(i <= index)
            dataOut[i] = dataIn[i];
          else
            dataOut[i] = 1'b0;
          end if;
     
     end

Author: TienNguyen (Guest)
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Thanks!

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