EmbDev.net

Forum: FPGA, VHDL & Verilog Excess 3 to gray code using verilog


Author: Kamal (Guest)
Posted on:

Rate this post
0 useful
not useful
I started working on Verilog since last night(less than 24 hours)
I'm trying to write a code for 4bit excess3 to gray code converter

i came up with this code but since I'm beginner i need your help to know 
what's my mistake
module ex3togry (A, B, C, D, , W, X, Y, Z,);
  input A,B,C,D;
  output X,W,Y,Z;
assign W= (A && B) || (A && C && D);
assign X= A || (B && C && D);
assign Y= (~B && ~ C && ~D) || ( B && D) || ( B && C);
assign Z= ~C;
endmodule

module converter3(Exin, Gout)
input [3:0] Exin;
output [3:0] Gout];

ex3togry FB0 (A [0] ,B[0],C[0],D[0],W[0] , X[0], Y[0], Z[0] );
ex3togry FB1 ( A[1],B[1],C[1],D[0],W[1] , X[1] , Y[1], Z[1]);
ex3togry FB2 ( A[2],B[2],C[2],D[2],W[2], X[2], Y[2], Z[2]);
ex3togry FB3 ( A[3],B[3],C[3],D[3],W[3], X[3] Y[3], Z [3] );
endmodule

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig