Forum: FPGA, VHDL & Verilog qsys and user design

von mike (Guest)

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hi everyone,

I am a beginner , i would like to know whether it is possible to connect 
qsys component + user design and successfully synthesis in an altera 
fpga. if yes, i see sop,pos and ready signals at qsys modules. how to 
deal with these signals. should i simply write a logic to decode these 
so that my design understands it.

my task is->

test pattern generator(qsys ip )-> edge detect(my design)->clocked video 
output(qsys ip)->displayport(qsys ip).

looking for your inputs:)

von Strubi (Guest)

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Why on earth would you want to use the Qsys crap as a beginner? (pardon 
my bluntness). Start small, keep it simple and remember that your best 
friend is a robust simulator. Qsys might pay off at a point where you 
need to integrate a complex CPU, but even that is questionable.

von C.G. (Guest)

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...can you put your edge detect design in a qsys component and insert 
this into your existing qsys system. You probably want to give that 
component a avalon master or slave interface or some conduits, depending 
on your design, so it can interact with the other qsys components via 
the avalon fabric. I dont say it is easy but that would probably work. 
BUT implementing a video and pattern generator is not so hard to do 
without the qsys stuff. There are dozens of example designs for that to 
get some inspiration how this can be accomplished.


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