Forum: FPGA, VHDL & Verilog NAND with x input

von LE DUC LOC (Guest)

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Hi all,

I have a problem when model my schematic.
I have 2 Nand device with one output is input of another one.
So every time my testbench is on, the value in the output of them are 
1'bx, so it made their output always 1'bx.

Can anyone provide me some solution to made the output of them.

Thank you very much.

von ossi-2 (Guest)

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Forcing the other inputs of the NANDs to 0 shoud set their outputs to 1 
so that you have a defined state from that moment on. The X signals in 
your case just reflect the fact that you didn't bring the Flip-Flop into 
a defined state in the beginning.


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