EmbDev.net

Forum: FPGA, VHDL & Verilog PS/2 module with LCD


Author: Luis G. (blasterfire)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hello, I have this project where I have to interact with the PS/2 module 
(a keyboard) and when I type the letters in the keyboard those must be 
shown in the LCD of the board.

I made a state machine where I tried to said that when I type a letter 
it must be held in a register until I let the button go and compare the 
break code with the letter registered and then that data must be gone to 
a case block where I wanna put all the possible cases of the letters to 
be shown in the LCD display.

But it doesn't work, it is recognizing the letter typed because I 
connected it to a 6-seg display, but the LCD doesn't show anything, can 
anyone help me?

Author: Luis G. (blasterfire)
Posted on:
Attached files:

Rate this post
0 useful
not useful
This is the whole project, in case anyone wants to help me

Author: -gb- (Guest)
Posted on:

Rate this post
0 useful
not useful
More Information please! What kind of Display? Which FPGA Board?

Author: Luis G. (blasterfire)
Posted on:

Rate this post
0 useful
not useful
it is a 16x2 LCD display, and the board is a DE0 Terasic Altera, the 
device is a Cyclone III EP3C16F484C6N

Author: -gb- (Guest)
Posted on:

Rate this post
0 useful
not useful
OK, i don't know verilog, sorry.

I would look at the Display-Datasheet and at the IO-Connections of 
Display and FPGA, how is ist connected? Parallel Bus or serial 
Interface? Which commands must be sent? Are the Voltages correct?. So 
first try to display any static Character on the Display.

Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
And then I would try to read a key (scancode) from a PS/2 keyboard.
And then I would convert the scancode to an ASCII character.
And then I would hand over that key to the display component.

So the most important process is to split up the "big problem" in 
several "small problems" that can be solved each one after (and 
independent from) the other. The debugging on this level is done solely 
by the simulator.

And when each one of that designs is running stand alone (at least in 
simulation, better if on real hardware also) , then it is fairly simple 
to connect them together to one big design.
This process is called "Divide et impera".

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.