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Forum: FPGA, VHDL & Verilog output comes after 1.2 sec delay after Power ON


Author: Naveedishtiaq N. (Company: Comsats) (naveed)
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hi ,
I am using XC6SLX9-2TQG144I  Spartan 6 device.

The problem i am facing problem regarding delay in output signals that 
are PWM_out and Clock _out . The output is dependent upon input Clock 
that is 2.097152 MHz.

The simulation doesnot show any delay but the actual hardware has timing 
issue. I dont know why ? My code is attached

: Edited by User
Author: Naveedishtiaq N. (Company: Comsats) (naveed)
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the twr file of the above program is attached

Author: Naveedishtiaq N. (Company: Comsats) (naveed)
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the twx file of the above program is attached

Author: Naveedishtiaq N. (Company: Comsats) (naveed)
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The .ucf file is attached also

Author: -gb- (Guest)
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Well, i wrote the Testbench ... and made an Screenshot.

It seems that you need an Reset to start the PWM? And after that, the 
PWM stays at '1' for all Time? Did you understand what a PWM does? Or 
post your Testbench file.

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