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Forum: FPGA, VHDL & Verilog set_input_delay And set_output_delay .SDC Constraints


Author: Ahmed Abbasi (Guest)
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Hello! I have little familiarity with the set_input_delay and 
set_output_delay SDC and was whether the following commands would 
correctly constrain the inputs.

WHAT THE DIAGRAM SHOWS : I have an 8-bit port on a Video Decoder which 
outputs data to the FPGA.The clock used in the FPGA is output from the 
same device.The device is configured to change its data on the falling 
edge of the clock.
The device opertes on a 27 Mhz clock i.e a period of 37.037 ns.
The datasheet lists T5 as Output Hold Time and gives a minimum Value of 
10ns.
The datasheet lists T6 as Output Delay Time and gives a maximum Value of 
25ns.
So, I conclude that with respect to the falling edge of the clock, the 
data l begins to change 10ns after falling edge and regains stability 
15ns later.Is this what the diagram depicts?

If so, I think the constrains that specify this should be :

create_clock -period 37.037 -name clkvin; #virtual clock for input 
constraint
set_input_delay -clock clkvin -max 25 [get_ports sdr_data*] -clock_fall
set_input_delay -clock clkvin -min 10 [get_ports sdr_data*] -clock_fall

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