Forum: FPGA, VHDL & Verilog FSM coding in VHDL

von Tarun M. (Company: NITK) (trmittal24)

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What type of VHDL coding is better for a FSM.
3 processes or 1 process?

von Duke Scarring (Guest)

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I prefer 2 process.

von Lothar M. (lkmiller) (Moderator)

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Usually I do it with 1 and a wait until rising_edge();

In few cases I use 2 processes, but nearly never.I have 3 of them...


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