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Forum: FPGA, VHDL & Verilog Error problem


Author: newProgrammer (Guest)
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Hi,

I am new to VHDL programming. This is the code I have written for 
dmux_1_to_4:

library ieee;
use ieee.std_logic_1164.all;

entity DMUX_1_to_4 is
port (
      data_in: in   std_logic;
      s : in     std_logic_vector(1 to 0);
      data_out : out   std_logic_vector(3 to 0)
     );
end entity;

architecture behaviour of DMUX_1_to_4 is
begin
  process(data_in, s)
  begin
    data_out <= "0000";
    case s is
      when "00" => data_out(0) <= data_in;
      when "01" => data_out(1) <= data_in;
      when "10" => data_out(2) <= data_in;
      when "11" => data_out(3) <= data_in;
      when others => null;
    end case;
  end process;
end architecture behaviour;

And I am getting this 14 error:

-- Compiling architecture behaviour of DMUX_1_to_4
** Error (suppressible): C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(16): 
(vcom-1272) Length of expected is 0; length of actual is 4.
** Error (suppressible): C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(18): 
(vcom-1272) Length of expected is 0; length of actual is 2.
** Error (suppressible): C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(19): 
(vcom-1272) Length of expected is 0; length of actual is 2.
** Error (suppressible): C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(20): 
(vcom-1272) Length of expected is 0; length of actual is 2.
** Error (suppressible): C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(21): 
(vcom-1272) Length of expected is 0; length of actual is 2.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(18): (vcom-1319) Case 
statement choice (string literal) length 2 is not equal to required 
length 0.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(19): (vcom-1319) Case 
statement choice (string literal) length 2 is not equal to required 
length 0.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(20): (vcom-1319) Case 
statement choice (string literal) length 2 is not equal to required 
length 0.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(21): (vcom-1319) Case 
statement choice (string literal) length 2 is not equal to required 
length 0.
** Warning: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(18): (vcom-1152) 
Index value 0 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Warning: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(19): (vcom-1152) 
Index value 1 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Warning: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(20): (vcom-1152) 
Index value 2 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Warning: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(21): (vcom-1152) 
Index value 3 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(21): (vcom-1152) Index 
value 3 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(20): (vcom-1152) Index 
value 2 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(19): (vcom-1152) Index 
value 1 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(18): (vcom-1152) Index 
value 0 is out of index range 3 to 0 (null array) of 
ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/intelFPGA_lite/16.1/DMUX_1_to_4.vhd(25): VHDL Compiler 
exiting

Where am I doing wrong? Thanks for any help!

Author: Lothar Miller (lkmiller) (Moderator)
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It goes DOWN from 3 to 0. So you should use DOWNTO for the range.

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