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Forum: FPGA, VHDL & Verilog tdo pin damagement


Author: vr7 (Guest)
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I have a problem when working with a virtex-7 xilinx fpga:

although all the connections are correct and the setup is reliable, it 
fails in chaining step in the impact. it is worth to mention that I test 
in the same manner by another fpga and everything is OK.

My test show an impedance of 3 Kilo Ohms between TDO pin and GND while 
this quantity is about 800 Kilo Ohms in a proper fpga of the same model.
This is the only difference observed between the damaged fpga and the 
proper one.


-I'd like to know if we can conclude this pin has been damaged?

- Could it be repaired anyway?

- Is there any other solution to chain and debug this fpga?

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