EmbDev.net

Forum: FPGA, VHDL & Verilog DMA with AXI lite interfaces


Author: Sai S. (Company: sssihl) (shashidhar)
Posted on:

Rate this post
0 useful
not useful
HI there,

Is it possible to use DMA with AXI-lite interfaces in IP integrator?

Author: Marc (Guest)
Posted on:

Rate this post
1 useful
not useful
Yes this works.

In a project i'm using an axi lite slave peripheral and a second 
hardware Block with full axi which is connected to the PS slave port is 
copying the data from the axi lite regs to ddr ram.

In Vivado HLS it is quite easy to implement a dma engine with full axi 
and bursts.

Author: Sai S. (Company: sssihl) (shashidhar)
Posted on:

Rate this post
0 useful
not useful
Hi
Thanks for the reply.

Suppose if I generate an IP core (with AXI lite interface) using Xilinx 
system generator design flow, still I should be able to use DMA, right?

Thanks in advance

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.