HI there, Is it possible to use DMA with AXI-lite interfaces in IP integrator?
Yes this works. In a project i'm using an axi lite slave peripheral and a second hardware Block with full axi which is connected to the PS slave port is copying the data from the axi lite regs to ddr ram. In Vivado HLS it is quite easy to implement a dma engine with full axi and bursts.
Hi Thanks for the reply. Suppose if I generate an IP core (with AXI lite interface) using Xilinx system generator design flow, still I should be able to use DMA, right? Thanks in advance