Forum: FPGA, VHDL & Verilog Clock manipulations without DCM

Author: Mark Hubner (Company: None) (marcvs)
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Hi, I'm Mark and I'm a VHDL newbie.
I need to generate 2 different signals from a 100 Mhz clock:

The first one will have 78 Mhz frequency and 50% Duty Cycle.
The second one 78 Mhz f and 70% DC.

I can't use DCM for this, just counters.

I attached a vhd source with a clock filter, I used this to get a 25 Mhz 
signal from a 100 Mhz clock with 50% D.C. It works fine, but it won't 
work as expected if the division between frequency_in and frequency_out 
is near 1, like in the 100/78 case.

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Clocks in FPGAs are generated by clock managers. Always.

That jittery derivative (named clock_out in your case) generated with a 
counter may be used as clock enables, but never ever as real clock.

Just read the manual of your FPGA. Chapter "Clocking".


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