Debugging with the J-Link Debugger and a CycloneV SoC

Hello list,

here is a small tutorial for how to Bare Metal debug with a
J-Link Debugger and a Cyclone V SoC on a Altera DE1-SoC target.

The Golden Hardware Reference Design (GHRD) for the
Altera DE1-SoC can be find here:
http://www.emb4fun.de/fpga/de1socghrd/index.html

And the tutorial for the debugging itself here:
http://www.emb4fun.de/arm/de1socjldbg/index.html

The application is running in the external DDR RAM of the Cyclone V.
For the debugging DS-5 is not needed.

Best regards,
Michael