Signals are not getting U value

Tammy Guest #4828505
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I’m implementing IDEA algorithm using VHDL, I have a problem in my 
keygenerator module, when I run the simulator I get values U in all of 
the signals even though I assign other values to them.
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----------------------------------------------------------------------------------

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-- Company: 

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-- Engineer: 

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-- 

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-- Create Date:    17:00:11 12/06/2012 

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-- Design Name: 

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-- Module Name:    key_generator - Behavioral 

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-- Project Name: 

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-- Target Devices: 

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-- Tool versions: 

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-- Description: 

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--

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-- Dependencies: 

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--

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-- Revision: 

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-- Revision 0.01 - File Created

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-- Additional Comments: 

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--

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----------------------------------------------------------------------------------

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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--use IEEE.NUMERIC_STD.ALL;

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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity keygenerator is

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    Port ( round : in  STD_LOGIC_VECTOR (3 downto 0);

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           key : in  STD_LOGIC_VECTOR (127 downto 0);

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           keyout1 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout2 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout3 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout4 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout5 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout6 : out  STD_LOGIC_VECTOR (15 downto 0));

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end keygenerator;

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architecture Behavioral of keygenerator is

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  SIGNAL key0 : std_logic_vector (127 downto 0);

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  SIGNAL key1 : std_logic_vector (127 downto 0);

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  SIGNAL key2 : std_logic_vector (127 downto 0);

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  SIGNAL key3 : std_logic_vector (127 downto 0);

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  SIGNAL key4 : std_logic_vector (127 downto 0);

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  SIGNAL key5 : std_logic_vector (127 downto 0);

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  SIGNAL key6 : std_logic_vector (95 downto 0);

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  signal output : std_logic_vector (95 downto 0);

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begin

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  process (round, key)

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  begin

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    key0 <= key;

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    key1 <= key0(102 downto 0) & key0(127 downto 103);

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    key2 <= key1(102 downto 0) & key1(127 downto 103);

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    key3 <= key2(102 downto 0) & key2(127 downto 103);

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    key4 <= key3(102 downto 0) & key3(127 downto 103);

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    key5 <= key4(102 downto 0) & key4(127 downto 103);

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    key6 <= key5(102 downto 7); 

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    case round is

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      when "0000" => output <= key0(127 downto 32);

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      when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);

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      when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);

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      when "0011" => output <= key2(95 downto 0);

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      when "0100" => output <= key3(127 downto 32);

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      when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);

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      when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);

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      when "0111" => output <= key5(95 downto 0);

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      when "1000" => output <= key6;

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      when others => output <= (others => 'X');

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    end case;

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  end process;

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  keyout6 <= output(15 downto 0);

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  keyout5 <= output(31 downto 16);

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  keyout4 <= output(47 downto 32);

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  keyout3 <= output(63 downto 48);

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  keyout2 <= output(79 downto 64);

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  keyout1 <= output(95 downto 80);

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end Behavioral;


That's my testbench:
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--------------------------------------------------------------------------------

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-- Company: 

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-- Engineer:

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--

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-- Create Date:   18:59:37 12/12/2016

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-- Design Name:   

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-- Module Name:   /nfs/TUEIEDA/LabHDL/2016w/ga92xuv/submit/rcs1/tb_keygenerator.vhd

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-- Project Name:  idea_rcs1

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-- Target Device:  

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-- Tool versions:  

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-- Description:   

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-- 

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-- VHDL Test Bench Created by ISE for module: keygenerator

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-- 

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-- Dependencies:

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-- 

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-- Revision:

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-- Revision 0.01 - File Created

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-- Additional Comments:

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--

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-- Notes: 

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-- This testbench has been automatically generated using types std_logic and

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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

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-- that these types always be used for the top-level I/O of a design in order

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-- to guarantee that the testbench will bind correctly to the post-implementation 

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-- simulation model.

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--------------------------------------------------------------------------------

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LIBRARY ieee;

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USE ieee.std_logic_1164.ALL;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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--USE ieee.numeric_std.ALL;

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ENTITY tb_keygenerator IS

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END tb_keygenerator;

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ARCHITECTURE behavior OF tb_keygenerator IS 

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    -- Component Declaration for the Unit Under Test (UUT)

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    COMPONENT keygenerator

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    PORT(

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         round : IN  std_logic_vector(3 downto 0);

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         key : IN  std_logic_vector(127 downto 0);

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         keyout1 : OUT  std_logic_vector(15 downto 0);

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         keyout2 : OUT  std_logic_vector(15 downto 0);

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         keyout3 : OUT  std_logic_vector(15 downto 0);

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         keyout4 : OUT  std_logic_vector(15 downto 0);

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         keyout5 : OUT  std_logic_vector(15 downto 0);

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         keyout6 : OUT  std_logic_vector(15 downto 0)

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        );

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    END COMPONENT;

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   --Inputs

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   signal round : std_logic_vector(3 downto 0) := (others => '0');

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   signal key : std_logic_vector(127 downto 0) := (others => '0');

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   --Outputs

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   signal out1 : std_logic_vector(15 downto 0);

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   signal out2 : std_logic_vector(15 downto 0);

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   signal out3 : std_logic_vector(15 downto 0);

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   signal out4 : std_logic_vector(15 downto 0);

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   signal out5 : std_logic_vector(15 downto 0);

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   signal out6 : std_logic_vector(15 downto 0);

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   -- No clocks detected in port list. Replace <clock> below with 

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   -- appropriate port name 

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   constant I_period : time := 10 ns;

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BEGIN

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  -- Instantiate the Unit Under Test (UUT)

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   uut: keygenerator PORT MAP (

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          round => round,

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          key => key,

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          keyout1 => out1,

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          keyout2 => out2,

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          keyout3 => out3,

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          keyout4 => out4,

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          keyout5 => out5,

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          keyout6 => out6

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        );

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   -- Clock process definitions

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   I_process :process

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   begin

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    key <= X"12345678912345678912345678912345";

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    round <="1100";

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    wait for I_period/2;

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    key <= X"12345678912345678912345678912345";

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    round <="1001";

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    wait for I_period/2;

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   end process;

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END;
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Achim S. Guest #4828538
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The assignment to a signal inside a process is not executed at the line 
where the assignment is written but at the end of the process. So if you 
write

    key0 <= key;

inside a process, then key0 still holds its former value (i.e. "U"s) 
until the process is at its end. Therefor in the next line

       key1 <= key0(102 downto 0) & key0(127 downto 103);

you assign "U"s to key1 ....

Things would look different ...
- if you would make the assignments to key0 .. key6 outside of the 
process
- if you would extend the sensitivity list of your process
- if you would use variables for key0 .. key6 instead of signals (this 
is a good example to understand the differences between signals and 
variables)
- if you would use a process which is controlled by a clock edge

Is your key-generator really intended to run without any clock?
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Tammy Guest #4828576
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This is an assignment and we are supposed to run it without any clock.
I used variables instead of signals and I still get the same error.
That's my updated code:

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3


4
-- Uncomment the following library declaration if using

5
-- arithmetic functions with Signed or Unsigned values

6
--use IEEE.NUMERIC_STD.ALL;

7


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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity keygenerator is

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    Port ( round : in  STD_LOGIC_VECTOR (3 downto 0);

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           key : in  STD_LOGIC_VECTOR (127 downto 0);

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           keyout1 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout2 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout3 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout4 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout5 : out  STD_LOGIC_VECTOR (15 downto 0);

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           keyout6 : out  STD_LOGIC_VECTOR (15 downto 0));

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end keygenerator;

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architecture Behavioral of keygenerator is

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  shared variable key0 : std_logic_vector (127 downto 0);

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  shared variable key1 : std_logic_vector (127 downto 0);

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  shared variable key2 : std_logic_vector (127 downto 0);

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  shared variable key3 : std_logic_vector (127 downto 0);

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  shared variable key4 : std_logic_vector (127 downto 0);

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  shared variable key5 : std_logic_vector (127 downto 0);

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  shared variable key6 : std_logic_vector (95 downto 0);

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  signal output : std_logic_vector (95 downto 0);

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begin

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  process (round, key)

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  begin

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    key0 := key;

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    key1 := key0(102 downto 0) & key0(127 downto 103);

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    key2 := key1(102 downto 0) & key1(127 downto 103);

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    key3 := key2(102 downto 0) & key2(127 downto 103);

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    key4 := key3(102 downto 0) & key3(127 downto 103);

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    key5 := key4(102 downto 0) & key4(127 downto 103);

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    key6 := key5(102 downto 7); 

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    case round is

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      when "0000" => output <= key0(127 downto 32);

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      when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);

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      when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);

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      when "0011" => output <= key2(95 downto 0);

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      when "0100" => output <= key3(127 downto 32);

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      when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);

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      when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);

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      when "0111" => output <= key5(95 downto 0);

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      when "1000" => output <= key6;

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      when others => output <= (others => 'X');

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    end case;

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  end process;

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  keyout6 <= output(15 downto 0);

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  keyout5 <= output(31 downto 16);

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  keyout4 <= output(47 downto 32);

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  keyout3 <= output(63 downto 48);

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  keyout2 <= output(79 downto 64);

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  keyout1 <= output(95 downto 80);

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end Behavioral;
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