EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL Code for 'String Parsing' circuit


von Omar (Guest)


Attached files:

Rate this post
0 useful
not useful
I am designing a VHDL combinational block that takes in a list of 8 
ASCII characters as input and replaces the non-numeral characters with a 
dash '-', then rearranges the list to have the numerals on one side and 
'-'s on the other.

Example input and output:

Input: d126r24!                      Output: ---12246

Here's my source code:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
5
entity module1 is
6
  port (list1: IN string (1 to 8);
7
        list2: OUT string (1 to 8));
8
end entity;
9
10
architecture behavior of module1 is
11
signal temp: string (1 to 8);
12
13
begin
14
15
process (list1)
16
variable a: integer:= 1;
17
variable b: integer:= 8;
18
variable c: string (1 to 8);
19
begin
20
21
for i in 1 to 8 loop
22
  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then
23
    c(a):= list1(i);
24
    if (a < 8) then
25
      a := a + 1;
26
    end if;
27
  else
28
    c(b) <= '-';
29
    if (b > 1) then
30
      b := b - 1;
31
    end if;
32
  end if;
33
end loop;
34
35
temp <= c;
36
end process;
37
list2 <= temp;
38
end behavior;

testbench:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
5
entity tb_module1 is
6
end entity;
7
8
architecture behavior of tb_module1 is
9
component module1
10
  port (list1: IN string (1 to 8);
11
        list2: OUT string (1 to 8));
12
end component;
13
14
signal list1, list2: string (1 to 8);
15
begin
16
DUT: module1 port map (list1 => list1, list2 => list2);
17
18
process
19
begin
20
wait for 0 ns;
21
list1 <= "12345678";
22
wait for 10 ns;
23
list1 <= "001122nn";
24
wait for 10 ns;
25
end process;
26
end behavior;

They compile fine but simulation gives me this error in the image 
attached. I cannot understand why this error is happening! It keeps 
saying that my index is out of range...

von Klakx (Guest)


Rate this post
0 useful
not useful
Maybe it is only this: c(b) <= '-'; should be c(b):='-';

von Omar (Guest)


Attached files:

Rate this post
0 useful
not useful
That still did not fix the problem. I modified the code to :
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
5
entity module1 is
6
  port (list1: IN string (1 to 8);
7
        list2: OUT string (1 to 8));
8
end entity;
9
10
architecture behavior of module1 is
11
signal temp: string (1 to 8);
12
13
begin
14
15
process (list1)
16
variable a: integer:= 1;
17
variable b: integer:= 8;
18
variable c: string (1 to 8);
19
begin
20
21
for i in 1 to 8 loop
22
  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then
23
    c(a):= list1(i);
24
    a := a + 1;
25
  else
26
    c(b) := '-';
27
    b := b - 1;
28
  end if;
29
end loop;
30
31
temp <= c;
32
end process;
33
list2 <= temp;
34
end behavior;

I still get an index out of range error as my attached capture shows. 
Please help me understand...

: Edited by Moderator
von Klakx (Guest)


Rate this post
0 useful
not useful
in the 2nd use of the process at 10ns ur variables a,b are not reseted. 
Initialize them at the beginning

von Omar (Guest)


Rate this post
0 useful
not useful
I thougjt initializing them at the beginning of the process does that? 
Doesn't that happen everytime the process is triggered? Or is it only 
the block after 'begin' that gets re executed?

Thanks O will try that.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.