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Forum: FPGA, VHDL & Verilog VHDL Code for 'String Parsing' circuit


Author: Omar (Guest)
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I am designing a VHDL combinational block that takes in a list of 8 
ASCII characters as input and replaces the non-numeral characters with a 
dash '-', then rearranges the list to have the numerals on one side and 
'-'s on the other.

Example input and output:

Input: d126r24!                      Output: ---12246

Here's my source code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity module1 is
  port (list1: IN string (1 to 8);
        list2: OUT string (1 to 8));
end entity;

architecture behavior of module1 is
signal temp: string (1 to 8);

begin

process (list1)
variable a: integer:= 1;
variable b: integer:= 8;
variable c: string (1 to 8);
begin

for i in 1 to 8 loop
  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then
    c(a):= list1(i);
    if (a < 8) then
      a := a + 1;
    end if;
  else
    c(b) <= '-';
    if (b > 1) then
      b := b - 1;
    end if;
  end if;
end loop;

temp <= c;
end process;
list2 <= temp;
end behavior;

testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_module1 is
end entity;

architecture behavior of tb_module1 is
component module1
  port (list1: IN string (1 to 8);
        list2: OUT string (1 to 8));
end component;

signal list1, list2: string (1 to 8);
begin
DUT: module1 port map (list1 => list1, list2 => list2);

process
begin
wait for 0 ns;
list1 <= "12345678";
wait for 10 ns;
list1 <= "001122nn";
wait for 10 ns;
end process;
end behavior;

They compile fine but simulation gives me this error in the image 
attached. I cannot understand why this error is happening! It keeps 
saying that my index is out of range...

Author: Klakx (Guest)
Posted on:

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Maybe it is only this: c(b) <= '-'; should be c(b):='-';

Author: Omar (Guest)
Posted on:
Attached files:

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That still did not fix the problem. I modified the code to :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity module1 is
  port (list1: IN string (1 to 8);
        list2: OUT string (1 to 8));
end entity;

architecture behavior of module1 is
signal temp: string (1 to 8);

begin

process (list1)
variable a: integer:= 1;
variable b: integer:= 8;
variable c: string (1 to 8);
begin

for i in 1 to 8 loop
  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then
    c(a):= list1(i);
    a := a + 1;
  else
    c(b) := '-';
    b := b - 1;
  end if;
end loop;

temp <= c;
end process;
list2 <= temp;
end behavior;

I still get an index out of range error as my attached capture shows. 
Please help me understand...

: Edited by Moderator
Author: Klakx (Guest)
Posted on:

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in the 2nd use of the process at 10ns ur variables a,b are not reseted. 
Initialize them at the beginning

Author: Omar (Guest)
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I thougjt initializing them at the beginning of the process does that? 
Doesn't that happen everytime the process is triggered? Or is it only 
the block after 'begin' that gets re executed?

Thanks O will try that.

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