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Forum: FPGA, VHDL & Verilog VHDL Code for 'String Parsing' circuit


VHDL Code for 'String Parsing' circuit
von Omar (Guest)

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I am designing a VHDL combinational block that takes in a list of 8 
ASCII characters as input and replaces the non-numeral characters with a 
dash '-', then rearranges the list to have the numerals on one side and 
'-'s on the other.

Example input and output:

Input: d126r24!                      Output: ---12246

Here's my source code:

1
library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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entity module1 is

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  port (list1: IN string (1 to 8);

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        list2: OUT string (1 to 8));

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end entity;

9
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architecture behavior of module1 is

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signal temp: string (1 to 8);

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begin

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process (list1)

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variable a: integer:= 1;

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variable b: integer:= 8;

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variable c: string (1 to 8);

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begin

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for i in 1 to 8 loop

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  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then

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    c(a):= list1(i);

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    if (a < 8) then

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      a := a + 1;

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    end if;

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  else

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    c(b) <= '-';

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    if (b > 1) then

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      b := b - 1;

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    end if;

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  end if;

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end loop;

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temp <= c;

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end process;

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list2 <= temp;

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end behavior;


testbench:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

4
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entity tb_module1 is

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end entity;

7
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architecture behavior of tb_module1 is

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component module1

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  port (list1: IN string (1 to 8);

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        list2: OUT string (1 to 8));

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end component;

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signal list1, list2: string (1 to 8);

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begin

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DUT: module1 port map (list1 => list1, list2 => list2);

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process

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begin

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wait for 0 ns;

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list1 <= "12345678";

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wait for 10 ns;

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list1 <= "001122nn";

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wait for 10 ns;

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end process;

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end behavior;


They compile fine but simulation gives me this error in the image 
attached. I cannot understand why this error is happening! It keeps 
saying that my index is out of range...

  


  




  

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    Re: VHDL Code for 'String Parsing' circuit
  


  

    

      von
      
        Klakx (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Maybe it is only this: c(b) <= '-'; should be c(b):='-';

  


  




  

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    Re: VHDL Code for 'String Parsing' circuit
  


  

    

      von
      
        Omar (Guest)
      
      


      
    


    

      
    

    

    

      

      

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That still did not fix the problem. I modified the code to :

1
library ieee;

2
use ieee.std_logic_1164.all;

3
use ieee.numeric_std.all;

4
5
entity module1 is

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  port (list1: IN string (1 to 8);

7
        list2: OUT string (1 to 8));

8
end entity;

9
10
architecture behavior of module1 is

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signal temp: string (1 to 8);

12
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begin

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process (list1)

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variable a: integer:= 1;

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variable b: integer:= 8;

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variable c: string (1 to 8);

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begin

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for i in 1 to 8 loop

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  if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then

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    c(a):= list1(i);

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    a := a + 1;

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  else

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    c(b) := '-';

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    b := b - 1;

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  end if;

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end loop;

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temp <= c;

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end process;

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list2 <= temp;

34
end behavior;


I still get an index out of range error as my attached capture shows. 
Please help me understand...

  


  



  

  
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    Re: VHDL Code for 'String Parsing' circuit
  


  

    

      von
      
        Klakx (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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in the 2nd use of the process at 10ns ur variables a,b are not reseted. 
Initialize them at the beginning

  


  




  

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    Re: VHDL Code for 'String Parsing' circuit
  


  

    

      von
      
        Omar (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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I thougjt initializing them at the beginning of the process does that? 
Doesn't that happen everytime the process is triggered? Or is it only 
the block after 'begin' that gets re executed?

Thanks O will try that.

  


  




  

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