Forum: FPGA, VHDL & Verilog DDR2 connecting

von Jost (Guest)

Rate this post
0 useful
not useful

I am designing a board with FPGA and DDR2 memory. I am using Lattice XP2 
chip with integrated blocks for interfacing DDR memory. However in 
datasheets I cannot find information about how addressing timings work 
and to which pins should address lines be connected. Fast I/O's are only 
for data lines.
Can somebody point me in the right direction here? Where can I get more 
information about this topic?

Regards, Jost


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.