I am fairly new to FPGA/Hardware design, so pardon if the question isn't 
appropriate for this forum. This question is pertaining to approaches 
available for automating validation of testing any combinational circuit 
in a synthesized implementation. I will try to explain it with an 
example

Say i have verilog module called ADD designed to add two numbers. Code 
for same is attached. Now as i understand, there are two methods with 
which i could validate the verilog module designed. They are using

    A. Simulation
    B. Synthesis.

For simulation purpose, i have used icarus verilog and created a test 
module that would instantiate the adder module and feed it various 
values and check the result with values computed. This is just provided 
for an illustration. Obviously for different circuits the test bench and 
testing method on simulation would vary.

Now for synthesized implementation, i am planning to use Xilinx FPGA. As 
i understand, we cannot use timing controls like #1 in the synthesized 
implementation. One approach, i could think of is creating a Look up 
table contain all test cases input and expected output and have it as 
part of the design. Run a counter and use the LSB bits of the counter to 
decide the test input for a given clock and check the output, in the 
event
of difference, write into a flip flop whose output would be used to 
turn-off a LED. Thus i could check whether the design has passed all the 
test conditions provided based on LED output status.

I am wondering if there are better approaches for performing validation 
of a synthesized implementation. For instance

A. Is there a way by which say, test inputs are available in a PC and 
can be streamed and generated output can be fed back to a file in PC.

B. Is there a way to mimic timing sequence control available in 
simulation and get tests done in synthesized implementation apart from 
using counters.

As i am a newbie to this, i am wondering how is this problem tackled in 
general. Any links to reference material that i could read through would 
be highly appreciated.