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Checking the validity of std_logic_vector value @testbench
von VHDL learner (Guest)

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Hi Experts,

what is the easiest way to check whether a std_logic_vector value has 
invalid/uninitialized bit(s) in it (such as 'X', 'U', 'Z'). VHDL-2008 
would be okay.

Regards...

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Re: Checking the validity of std_logic_vector value @testbench
von Duke Scarring (Guest)

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I would write a function:
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    function has_X( value : std_logic_vector) return boolean is

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    begin

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        for index in value'range loop

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            if value( index) = 'X' then

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                return true;

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            end if;

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        end loop;

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        return false;

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    end function has_X;


Duke

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Re: Checking the validity of std_logic_vector value @testbench
von Ottmar (Guest)

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This function is already defined in std_logic_1164.

Excerpt:
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    FUNCTION Is_X ( s : std_logic_vector  ) RETURN  BOOLEAN IS

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    BEGIN

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        FOR i IN s'RANGE LOOP

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            CASE s(i) IS

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                WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;

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                WHEN OTHERS => NULL;

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            END CASE;

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        END LOOP;

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        RETURN FALSE;

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    END;

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