Forum: FPGA, VHDL & Verilog arbiter using verilog

von ANURAG S. (Company: student) (anurag3939)

Rate this post
0 useful
not useful
hello everyone,
             i have given an assignment in which i want to design an 
arbiter who takes input from a fifo. FIFO has width of 32 bit and we 
need to divide these bits into sub packets of where first two bits 
contains the head or tail or normal or no flit of fifo and next three 
bits contains the addres of grant of arbiter.... if anyone have any idea 
plzzz reply :)


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.